2 * (C) Copyright 2010-2014
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/funcmux.h>
12 #include <asm/arch/tegra.h>
13 #include <asm/arch-tegra/board.h>
14 #include <asm/arch-tegra/pmc.h>
15 #include <asm/arch-tegra/sys_proto.h>
16 #include <asm/arch-tegra/warmboot.h>
18 DECLARE_GLOBAL_DATA_PTR;
21 /* UARTs which we can enable */
30 #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
31 defined(CONFIG_TEGRA114)
33 * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
34 * so we are using this value to identify memory size.
36 unsigned int query_sdram_size(void)
38 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
41 reg = readl(&pmc->pmc_scratch20);
42 debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
44 #if defined(CONFIG_TEGRA20)
45 /* bits 30:28 in OdmData are used for RAM size on T20 */
48 switch ((reg) >> 28) {
50 return 0x10000000; /* 256 MB */
54 return 0x20000000; /* 512 MB */
56 return 0x40000000; /* 1GB */
58 #else /* Tegra30/Tegra114 */
59 /* bits 31:28 in OdmData are used for RAM size on T30 */
60 switch ((reg) >> 28) {
64 return 0x10000000; /* 256 MB */
66 return 0x20000000; /* 512 MB */
68 return 0x30000000; /* 768 MB */
70 return 0x40000000; /* 1GB */
72 return 0x7ff00000; /* 2GB - 1MB */
77 #include <asm/arch/mc.h>
79 /* Read the RAM size directly from the memory controller */
80 unsigned int query_sdram_size(void)
82 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
85 size_mb = readl(&mc->mc_emem_cfg);
86 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
88 return size_mb * 1024 * 1024;
94 /* We do not initialise DRAM here. We just query the size */
95 gd->ram_size = query_sdram_size();
99 #ifdef CONFIG_DISPLAY_BOARDINFO
102 printf("Board: %s\n", sysinfo.board_string);
105 #endif /* CONFIG_DISPLAY_BOARDINFO */
107 static int uart_configs[] = {
108 #if defined(CONFIG_TEGRA20)
109 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
110 FUNCMUX_UART1_UAA_UAB,
111 #elif defined(CONFIG_TEGRA_UARTA_GPU)
113 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
116 FUNCMUX_UART1_IRRX_IRTX,
122 #elif defined(CONFIG_TEGRA30)
123 FUNCMUX_UART1_ULPI, /* UARTA */
128 #elif defined(CONFIG_TEGRA114)
132 FUNCMUX_UART4_GMI, /* UARTD */
135 FUNCMUX_UART1_KBC, /* UARTA */
138 FUNCMUX_UART4_GPIO, /* UARTD */
144 * Set up the specified uarts
146 * @param uarts_ids Mask containing UARTs to init (UARTx)
148 static void setup_uarts(int uart_ids)
150 static enum periph_id id_for_uart[] = {
159 for (i = 0; i < UART_COUNT; i++) {
160 if (uart_ids & (1 << i)) {
161 enum periph_id id = id_for_uart[i];
163 funcmux_select(id, uart_configs[i]);
164 clock_ll_start_uart(id);
169 void board_init_uart_f(void)
171 int uart_ids = 0; /* bit mask of which UART ids to enable */
173 #ifdef CONFIG_TEGRA_ENABLE_UARTA
176 #ifdef CONFIG_TEGRA_ENABLE_UARTB
179 #ifdef CONFIG_TEGRA_ENABLE_UARTC
182 #ifdef CONFIG_TEGRA_ENABLE_UARTD
185 #ifdef CONFIG_TEGRA_ENABLE_UARTE
188 setup_uarts(uart_ids);
191 #ifndef CONFIG_SYS_DCACHE_OFF
192 void enable_caches(void)
194 /* Enable D-cache. I-cache is already enabled in start.S */