2 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra cache routines */
21 #include <asm/arch-tegra/ap.h>
22 #include <asm/arch/gp_padctrl.h>
24 void config_cache(void)
26 struct apb_misc_gp_ctlr *gp =
27 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
30 /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
32 "mrc p15, 0, r0, c1, c0, 1\n"
34 "mcr p15, 0, r0, c1, c0, 1\n");
36 /* Currently, only T114 needs this L2 cache change to boot Linux */
37 reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
38 if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
41 * Systems with an architectural L2 cache must not use the PL310.
42 * Config L2CTLR here for a data RAM latency of 3 cycles.
44 asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
47 asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));