2 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra SoC common clock control functions */
21 #include <asm/arch/clock.h>
22 #include <asm/arch/tegra.h>
23 #include <asm/arch-tegra/clk_rst.h>
24 #include <asm/arch-tegra/timer.h>
29 * This is our record of the current clock rate of each clock. We don't
30 * fill all of these in since we are only really interested in clocks which
33 static unsigned pll_rate[CLOCK_ID_COUNT];
36 * The oscillator frequency is fixed to one of four set values. Based on this
37 * the other clocks are set up appropriately.
39 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
46 /* return 1 if a peripheral ID is in range */
47 #define clock_type_id_isvalid(id) ((id) >= 0 && \
48 (id) < CLOCK_TYPE_COUNT)
50 char pllp_valid = 1; /* PLLP is set up correctly */
52 /* return 1 if a periphc_internal_id is in range */
53 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
56 /* number of clock outputs of a PLL */
57 static const u8 pll_num_clkouts[] = {
66 int clock_get_osc_bypass(void)
68 struct clk_rst_ctlr *clkrst =
69 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
72 reg = readl(&clkrst->crc_osc_ctrl);
73 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
76 /* Returns a pointer to the registers of the given pll */
77 static struct clk_pll *get_pll(enum clock_id clkid)
79 struct clk_rst_ctlr *clkrst =
80 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
82 assert(clock_id_is_pll(clkid));
83 return &clkrst->crc_pll[clkid];
86 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
87 u32 *divp, u32 *cpcon, u32 *lfcon)
89 struct clk_pll *pll = get_pll(clkid);
92 assert(clkid != CLOCK_ID_USB);
94 /* Safety check, adds to code size but is small */
95 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
97 data = readl(&pll->pll_base);
98 *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
99 *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
100 *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
101 data = readl(&pll->pll_misc);
102 *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
103 *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
108 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
109 u32 divp, u32 cpcon, u32 lfcon)
111 struct clk_pll *pll = get_pll(clkid);
115 * We cheat by treating all PLL (except PLLU) in the same fashion.
116 * This works only because:
117 * - same fields are always mapped at same offsets, except DCCON
118 * - DCCON is always 0, doesn't conflict
119 * - M,N, P of PLLP values are ignored for PLLP
121 data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
122 writel(data, &pll->pll_misc);
124 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
125 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
127 if (clkid == CLOCK_ID_USB)
128 data |= divp << PLLU_VCO_FREQ_SHIFT;
130 data |= divp << PLL_DIVP_SHIFT;
131 writel(data, &pll->pll_base);
133 /* calculate the stable time */
134 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
137 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
140 u32 *reg = get_periph_source_reg(periph_id);
145 value &= ~OUT_CLK_SOURCE_31_30_MASK;
146 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
148 value &= ~OUT_CLK_DIVISOR_MASK;
149 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
154 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
156 u32 *reg = get_periph_source_reg(periph_id);
158 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
159 source << OUT_CLK_SOURCE_31_30_SHIFT);
163 * Given the parent's rate and the required rate for the children, this works
164 * out the peripheral clock divider to use, in 7.1 binary format.
166 * @param divider_bits number of divider bits (8 or 16)
167 * @param parent_rate clock rate of parent clock in Hz
168 * @param rate required clock rate for this clock
169 * @return divider which should be used
171 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
174 u64 divider = parent_rate * 2;
175 unsigned max_divider = 1 << divider_bits;
178 do_div(divider, rate);
180 if ((s64)divider - 2 < 0)
183 if ((s64)divider - 2 >= max_divider)
189 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
191 struct clk_pll *pll = get_pll(clkid);
192 int data = 0, div = 0, offset = 0;
194 if (!clock_id_is_pll(clkid))
197 if (pllout + 1 > pll_num_clkouts[clkid])
200 div = clk_get_divider(8, pll_rate[clkid], rate);
205 /* out2 and out4 are in the high part of the register */
206 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
209 data = (div << PLL_OUT_RATIO_SHIFT) |
210 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
211 clrsetbits_le32(&pll->pll_out[pllout >> 1],
212 PLL_OUT_RATIO_MASK << offset, data << offset);
218 * Given the parent's rate and the divider in 7.1 format, this works out the
219 * resulting peripheral clock rate.
221 * @param parent_rate clock rate of parent clock in Hz
222 * @param divider which should be used in 7.1 format
223 * @return effective clock rate of peripheral
225 static unsigned long get_rate_from_divider(unsigned long parent_rate,
230 rate = (u64)parent_rate * 2;
231 do_div(rate, divider + 2);
235 unsigned long clock_get_periph_rate(enum periph_id periph_id,
236 enum clock_id parent)
238 u32 *reg = get_periph_source_reg(periph_id);
240 return get_rate_from_divider(pll_rate[parent],
241 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
245 * Find the best available 7.1 format divisor given a parent clock rate and
246 * required child clock rate. This function assumes that a second-stage
247 * divisor is available which can divide by powers of 2 from 1 to 256.
249 * @param divider_bits number of divider bits (8 or 16)
250 * @param parent_rate clock rate of parent clock in Hz
251 * @param rate required clock rate for this clock
252 * @param extra_div value for the second-stage divisor (not set if this
253 * function returns -1.
254 * @return divider which should be used, or -1 if nothing is valid
257 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
258 unsigned long rate, int *extra_div)
261 int best_divider = -1;
262 int best_error = rate;
264 /* try dividers from 1 to 256 and find closest match */
265 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
266 unsigned divided_parent = parent_rate >> shift;
267 int divider = clk_get_divider(divider_bits, divided_parent,
269 unsigned effective_rate = get_rate_from_divider(divided_parent,
271 int error = rate - effective_rate;
273 /* Given a valid divider, look for the lowest error */
274 if (divider != -1 && error < best_error) {
276 *extra_div = 1 << shift;
277 best_divider = divider;
281 /* return what we found - *extra_div will already be set */
286 * Adjust peripheral PLL to use the given divider and source.
288 * @param periph_id peripheral to adjust
289 * @param source Source number (0-3 or 0-7)
290 * @param mux_bits Number of mux bits (2 or 4)
291 * @param divider Required divider in 7.1 or 15.1 format
292 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
293 * for this peripheral)
295 static int adjust_periph_pll(enum periph_id periph_id, int source,
296 int mux_bits, unsigned divider)
298 u32 *reg = get_periph_source_reg(periph_id);
300 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
301 divider << OUT_CLK_DIVISOR_SHIFT);
304 /* work out the source clock and set it */
309 case MASK_BITS_31_30:
310 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
311 source << OUT_CLK_SOURCE_31_30_SHIFT);
314 case MASK_BITS_31_29:
315 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
316 source << OUT_CLK_SOURCE_31_29_SHIFT);
319 case MASK_BITS_31_28:
320 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
321 source << OUT_CLK_SOURCE_31_28_SHIFT);
332 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
333 enum clock_id parent, unsigned rate, int *extra_div)
335 unsigned effective_rate;
336 int mux_bits, divider_bits, source;
340 /* work out the source clock and set it */
341 source = get_periph_clock_source(periph_id, parent, &mux_bits,
344 divider = find_best_divider(divider_bits, pll_rate[parent],
349 assert(divider >= 0);
350 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
352 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
353 get_periph_source_reg(periph_id),
354 readl(get_periph_source_reg(periph_id)));
356 /* Check what we ended up with. This shouldn't matter though */
357 effective_rate = clock_get_periph_rate(periph_id, parent);
359 effective_rate /= *extra_div;
360 if (rate != effective_rate)
361 debug("Requested clock rate %u not honored (got %u)\n",
362 rate, effective_rate);
363 return effective_rate;
366 unsigned clock_start_periph_pll(enum periph_id periph_id,
367 enum clock_id parent, unsigned rate)
369 unsigned effective_rate;
371 reset_set_enable(periph_id, 1);
372 clock_enable(periph_id);
374 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
377 reset_set_enable(periph_id, 0);
378 return effective_rate;
381 void clock_enable(enum periph_id clkid)
383 clock_set_enable(clkid, 1);
386 void clock_disable(enum periph_id clkid)
388 clock_set_enable(clkid, 0);
391 void reset_periph(enum periph_id periph_id, int us_delay)
393 /* Put peripheral into reset */
394 reset_set_enable(periph_id, 1);
398 reset_set_enable(periph_id, 0);
403 void reset_cmplx_set_enable(int cpu, int which, int reset)
405 struct clk_rst_ctlr *clkrst =
406 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
409 /* Form the mask, which depends on the cpu chosen (2 or 4) */
410 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
413 /* either enable or disable those reset for that CPU */
415 writel(mask, &clkrst->crc_cpu_cmplx_set);
417 writel(mask, &clkrst->crc_cpu_cmplx_clr);
420 unsigned clock_get_rate(enum clock_id clkid)
428 parent_rate = osc_freq[clock_get_osc_freq()];
429 if (clkid == CLOCK_ID_OSC)
432 pll = get_pll(clkid);
433 base = readl(&pll->pll_base);
435 /* Oh for bf_unpack()... */
436 rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
437 divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
438 if (clkid == CLOCK_ID_USB)
439 divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
441 divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
447 * Set the output frequency you want for each PLL clock.
448 * PLL output frequencies are programmed by setting their N, M and P values.
449 * The governing equations are:
450 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
451 * where Fo is the output frequency from the PLL.
452 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
453 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
454 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
456 * @param n PLL feedback divider(DIVN)
457 * @param m PLL input divider(DIVN)
458 * @param p post divider(DIVP)
459 * @param cpcon base PLL charge pump(CPCON)
460 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
461 * be overriden), 1 if PLL is already correct
463 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
469 pll = get_pll(clkid);
471 base_reg = readl(&pll->pll_base);
473 /* Set BYPASS, m, n and p to PLL_BASE */
474 base_reg &= ~PLL_DIVM_MASK;
475 base_reg |= m << PLL_DIVM_SHIFT;
477 base_reg &= ~PLL_DIVN_MASK;
478 base_reg |= n << PLL_DIVN_SHIFT;
480 base_reg &= ~PLL_DIVP_MASK;
481 base_reg |= p << PLL_DIVP_SHIFT;
483 if (clkid == CLOCK_ID_PERIPH) {
485 * If the PLL is already set up, check that it is correct
486 * and record this info for clock_verify() to check.
488 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
489 base_reg |= PLL_ENABLE_MASK;
490 if (base_reg != readl(&pll->pll_base))
492 return pllp_valid ? 1 : -1;
494 base_reg |= PLL_BASE_OVRRIDE_MASK;
497 base_reg |= PLL_BYPASS_MASK;
498 writel(base_reg, &pll->pll_base);
500 /* Set cpcon to PLL_MISC */
501 misc_reg = readl(&pll->pll_misc);
502 misc_reg &= ~PLL_CPCON_MASK;
503 misc_reg |= cpcon << PLL_CPCON_SHIFT;
504 writel(misc_reg, &pll->pll_misc);
507 base_reg |= PLL_ENABLE_MASK;
508 writel(base_reg, &pll->pll_base);
511 base_reg &= ~PLL_BYPASS_MASK;
512 writel(base_reg, &pll->pll_base);
517 void clock_ll_start_uart(enum periph_id periph_id)
519 /* Assert UART reset and enable clock */
520 reset_set_enable(periph_id, 1);
521 clock_enable(periph_id);
522 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
527 /* De-assert reset to UART */
528 reset_set_enable(periph_id, 0);
531 #ifdef CONFIG_OF_CONTROL
532 int clock_decode_periph_id(const void *blob, int node)
538 err = fdtdec_get_int_array(blob, node, "clocks", cell,
542 id = clk_id_to_periph_id(cell[1]);
543 assert(clock_periph_id_isvalid(id));
546 #endif /* CONFIG_OF_CONTROL */
548 int clock_verify(void)
550 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
551 u32 reg = readl(&pll->pll_base);
554 printf("Warning: PLLP %x is not correct\n", reg);
557 debug("PLLP %x is correct\n", reg);
561 void clock_init(void)
563 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
564 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
565 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
566 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
567 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
568 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
569 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
570 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
571 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
572 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
573 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
575 /* Do any special system timer/TSC setup */
579 static void set_avp_clock_source(u32 src)
581 struct clk_rst_ctlr *clkrst =
582 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
585 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
586 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
587 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
588 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
589 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
590 writel(val, &clkrst->crc_sclk_brst_pol);
595 * This function is useful on Tegra30, and any later SoCs that have compatible
596 * PLLP configuration registers.
598 void tegra30_set_up_pllp(void)
600 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
604 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
605 * run up to 275MHz. On power on, the default sytem clock source is set
606 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
607 * 408MHz which is beyond system clock's upper limit.
609 * The fix is to set the system clock to CLK_M before initializing PLLP,
610 * and then switch back to PLLP_OUT4, which has an appropriate divider
611 * configured, after PLLP has been configured
613 set_avp_clock_source(SCLK_SOURCE_CLKM);
616 * PLLP output frequency set to 408Mhz
617 * PLLC output frequency set to 228Mhz
619 switch (clock_get_osc_freq()) {
620 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
621 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
622 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
625 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
626 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
627 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
630 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
631 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
632 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
634 case CLOCK_OSC_FREQ_19_2:
637 * These are not supported. It is too early to print a
638 * message and the UART likely won't work anyway due to the
639 * oscillator being wrong.
644 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
647 /* Assert RSTN before enable */
648 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
649 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
650 /* Set divisor and reenable */
651 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
652 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
653 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
654 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
655 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
658 /* Assert RSTN before enable */
659 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
660 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
661 /* Set divisor and reenable */
662 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
663 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
664 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
665 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
666 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
668 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);