2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/pinmux.h>
12 /* return 1 if a pingrp is in range */
13 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
15 /* return 1 if a pmux_func is in range */
16 #define pmux_func_isvalid(func) \
17 (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
19 /* return 1 if a pin_pupd_is in range */
20 #define pmux_pin_pupd_isvalid(pupd) \
21 (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
23 /* return 1 if a pin_tristate_is in range */
24 #define pmux_pin_tristate_isvalid(tristate) \
25 (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
27 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
28 /* return 1 if a pin_io_is in range */
29 #define pmux_pin_io_isvalid(io) \
30 (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
32 /* return 1 if a pin_lock is in range */
33 #define pmux_pin_lock_isvalid(lock) \
34 (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
36 /* return 1 if a pin_od is in range */
37 #define pmux_pin_od_isvalid(od) \
38 (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
40 /* return 1 if a pin_ioreset_is in range */
41 #define pmux_pin_ioreset_isvalid(ioreset) \
42 (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
43 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
45 #ifdef TEGRA_PMX_HAS_RCV_SEL
46 /* return 1 if a pin_rcv_sel_is in range */
47 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
48 (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
49 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
50 #endif /* TEGRA_PMX_HAS_RCV_SEL */
51 #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
53 #define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
55 #if defined(CONFIG_TEGRA20)
57 #define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
58 #define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
60 #define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
61 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
63 #define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
64 #define TRI_SHIFT(grp) ((grp) % 32)
68 #define REG(pin) _R(0x3000 + ((pin) * 4))
70 #define MUX_REG(pin) REG(pin)
71 #define MUX_SHIFT(pin) 0
73 #define PULL_REG(pin) REG(pin)
74 #define PULL_SHIFT(pin) 2
76 #define TRI_REG(pin) REG(pin)
77 #define TRI_SHIFT(pin) 4
79 #endif /* CONFIG_TEGRA20 */
81 #define DRV_REG(group) _R(0x868 + ((group) * 4))
86 #define IO_RESET_SHIFT 8
87 #define RCV_SEL_SHIFT 9
89 #if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
90 /* This register/field only exists on Tegra114 and later */
91 #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
92 #define CLAMP_INPUTS_WHEN_TRISTATED 1
94 void pinmux_set_tristate_input_clamping(void)
96 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
100 val |= CLAMP_INPUTS_WHEN_TRISTATED;
105 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
107 u32 *reg = MUX_REG(pin);
111 if (func == PMUX_FUNC_DEFAULT)
114 /* Error check on pin and func */
115 assert(pmux_pingrp_isvalid(pin));
116 assert(pmux_func_isvalid(func));
118 if (func >= PMUX_FUNC_RSVD1) {
119 mux = (func - PMUX_FUNC_RSVD1) & 3;
121 /* Search for the appropriate function */
122 for (i = 0; i < 4; i++) {
123 if (tegra_soc_pingroups[pin].funcs[i] == func) {
132 val &= ~(3 << MUX_SHIFT(pin));
133 val |= (mux << MUX_SHIFT(pin));
137 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
139 u32 *reg = PULL_REG(pin);
142 /* Error check on pin and pupd */
143 assert(pmux_pingrp_isvalid(pin));
144 assert(pmux_pin_pupd_isvalid(pupd));
147 val &= ~(3 << PULL_SHIFT(pin));
148 val |= (pupd << PULL_SHIFT(pin));
152 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
154 u32 *reg = TRI_REG(pin);
157 /* Error check on pin */
158 assert(pmux_pingrp_isvalid(pin));
159 assert(pmux_pin_tristate_isvalid(tri));
162 if (tri == PMUX_TRI_TRISTATE)
163 val |= (1 << TRI_SHIFT(pin));
165 val &= ~(1 << TRI_SHIFT(pin));
169 void pinmux_tristate_enable(enum pmux_pingrp pin)
171 pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
174 void pinmux_tristate_disable(enum pmux_pingrp pin)
176 pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
179 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
180 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
185 if (io == PMUX_PIN_NONE)
188 /* Error check on pin and io */
189 assert(pmux_pingrp_isvalid(pin));
190 assert(pmux_pin_io_isvalid(io));
193 if (io == PMUX_PIN_INPUT)
194 val |= (io & 1) << IO_SHIFT;
196 val &= ~(1 << IO_SHIFT);
200 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
205 if (lock == PMUX_PIN_LOCK_DEFAULT)
208 /* Error check on pin and lock */
209 assert(pmux_pingrp_isvalid(pin));
210 assert(pmux_pin_lock_isvalid(lock));
213 if (lock == PMUX_PIN_LOCK_ENABLE) {
214 val |= (1 << LOCK_SHIFT);
216 if (val & (1 << LOCK_SHIFT))
217 printf("%s: Cannot clear LOCK bit!\n", __func__);
218 val &= ~(1 << LOCK_SHIFT);
225 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
230 if (od == PMUX_PIN_OD_DEFAULT)
233 /* Error check on pin and od */
234 assert(pmux_pingrp_isvalid(pin));
235 assert(pmux_pin_od_isvalid(od));
238 if (od == PMUX_PIN_OD_ENABLE)
239 val |= (1 << OD_SHIFT);
241 val &= ~(1 << OD_SHIFT);
247 static void pinmux_set_ioreset(enum pmux_pingrp pin,
248 enum pmux_pin_ioreset ioreset)
253 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
256 /* Error check on pin and ioreset */
257 assert(pmux_pingrp_isvalid(pin));
258 assert(pmux_pin_ioreset_isvalid(ioreset));
261 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
262 val |= (1 << IO_RESET_SHIFT);
264 val &= ~(1 << IO_RESET_SHIFT);
270 #ifdef TEGRA_PMX_HAS_RCV_SEL
271 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
272 enum pmux_pin_rcv_sel rcv_sel)
277 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
280 /* Error check on pin and rcv_sel */
281 assert(pmux_pingrp_isvalid(pin));
282 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
285 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
286 val |= (1 << RCV_SEL_SHIFT);
288 val &= ~(1 << RCV_SEL_SHIFT);
293 #endif /* TEGRA_PMX_HAS_RCV_SEL */
294 #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
296 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
298 enum pmux_pingrp pin = config->pingrp;
300 pinmux_set_func(pin, config->func);
301 pinmux_set_pullupdown(pin, config->pull);
302 pinmux_set_tristate(pin, config->tristate);
303 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
304 pinmux_set_io(pin, config->io);
305 pinmux_set_lock(pin, config->lock);
306 pinmux_set_od(pin, config->od);
307 pinmux_set_ioreset(pin, config->ioreset);
308 #ifdef TEGRA_PMX_HAS_RCV_SEL
309 pinmux_set_rcv_sel(pin, config->rcv_sel);
314 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
319 for (i = 0; i < len; i++)
320 pinmux_config_pingrp(&config[i]);
323 #ifdef TEGRA_PMX_HAS_DRVGRPS
325 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
327 #define pmux_slw_isvalid(slw) \
328 (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
330 #define pmux_drv_isvalid(drv) \
331 (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
333 #define pmux_lpmd_isvalid(lpm) \
334 (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
336 #define pmux_schmt_isvalid(schmt) \
337 (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
339 #define pmux_hsm_isvalid(hsm) \
340 (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
343 #define SCHMT_SHIFT 3
345 #define LPMD_MASK (3 << LPMD_SHIFT)
346 #define DRVDN_SHIFT 12
347 #define DRVDN_MASK (0x7F << DRVDN_SHIFT)
348 #define DRVUP_SHIFT 20
349 #define DRVUP_MASK (0x7F << DRVUP_SHIFT)
350 #define SLWR_SHIFT 28
351 #define SLWR_MASK (3 << SLWR_SHIFT)
352 #define SLWF_SHIFT 30
353 #define SLWF_MASK (3 << SLWF_SHIFT)
355 static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
357 u32 *reg = DRV_REG(grp);
360 /* NONE means unspecified/do not change/use POR value */
361 if (slwf == PMUX_SLWF_NONE)
364 /* Error check on pad and slwf */
365 assert(pmux_drvgrp_isvalid(grp));
366 assert(pmux_slw_isvalid(slwf));
370 val |= (slwf << SLWF_SHIFT);
376 static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
378 u32 *reg = DRV_REG(grp);
381 /* NONE means unspecified/do not change/use POR value */
382 if (slwr == PMUX_SLWR_NONE)
385 /* Error check on pad and slwr */
386 assert(pmux_drvgrp_isvalid(grp));
387 assert(pmux_slw_isvalid(slwr));
391 val |= (slwr << SLWR_SHIFT);
397 static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
399 u32 *reg = DRV_REG(grp);
402 /* NONE means unspecified/do not change/use POR value */
403 if (drvup == PMUX_DRVUP_NONE)
406 /* Error check on pad and drvup */
407 assert(pmux_drvgrp_isvalid(grp));
408 assert(pmux_drv_isvalid(drvup));
412 val |= (drvup << DRVUP_SHIFT);
418 static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
420 u32 *reg = DRV_REG(grp);
423 /* NONE means unspecified/do not change/use POR value */
424 if (drvdn == PMUX_DRVDN_NONE)
427 /* Error check on pad and drvdn */
428 assert(pmux_drvgrp_isvalid(grp));
429 assert(pmux_drv_isvalid(drvdn));
433 val |= (drvdn << DRVDN_SHIFT);
439 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
441 u32 *reg = DRV_REG(grp);
444 /* NONE means unspecified/do not change/use POR value */
445 if (lpmd == PMUX_LPMD_NONE)
448 /* Error check pad and lpmd value */
449 assert(pmux_drvgrp_isvalid(grp));
450 assert(pmux_lpmd_isvalid(lpmd));
454 val |= (lpmd << LPMD_SHIFT);
460 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
462 u32 *reg = DRV_REG(grp);
465 /* NONE means unspecified/do not change/use POR value */
466 if (schmt == PMUX_SCHMT_NONE)
469 /* Error check pad */
470 assert(pmux_drvgrp_isvalid(grp));
471 assert(pmux_schmt_isvalid(schmt));
474 if (schmt == PMUX_SCHMT_ENABLE)
475 val |= (1 << SCHMT_SHIFT);
477 val &= ~(1 << SCHMT_SHIFT);
483 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
485 u32 *reg = DRV_REG(grp);
488 /* NONE means unspecified/do not change/use POR value */
489 if (hsm == PMUX_HSM_NONE)
492 /* Error check pad */
493 assert(pmux_drvgrp_isvalid(grp));
494 assert(pmux_hsm_isvalid(hsm));
497 if (hsm == PMUX_HSM_ENABLE)
498 val |= (1 << HSM_SHIFT);
500 val &= ~(1 << HSM_SHIFT);
506 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
508 enum pmux_drvgrp grp = config->drvgrp;
510 pinmux_set_drvup_slwf(grp, config->slwf);
511 pinmux_set_drvdn_slwr(grp, config->slwr);
512 pinmux_set_drvup(grp, config->drvup);
513 pinmux_set_drvdn(grp, config->drvdn);
514 pinmux_set_lpmd(grp, config->lpmd);
515 pinmux_set_schmt(grp, config->schmt);
516 pinmux_set_hsm(grp, config->hsm);
519 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
524 for (i = 0; i < len; i++)
525 pinmux_config_drvgrp(&config[i]);
527 #endif /* TEGRA_PMX_HAS_DRVGRPS */