2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra114 pin multiplexing functions */
21 #include <asm/arch/tegra.h>
22 #include <asm/arch/pinmux.h>
24 struct tegra_pingroup_desc {
26 enum pmux_func funcs[4];
27 enum pmux_vddio vddio;
31 #define PMUX_MUXCTL_SHIFT 0
32 #define PMUX_PULL_SHIFT 2
33 #define PMUX_TRISTATE_SHIFT 4
34 #define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
35 #define PMUX_IO_SHIFT 5
36 #define PMUX_OD_SHIFT 6
37 #define PMUX_LOCK_SHIFT 7
38 #define PMUX_IO_RESET_SHIFT 8
39 #define PMUX_RCV_SEL_SHIFT 9
41 #define PGRP_HSM_SHIFT 2
42 #define PGRP_SCHMT_SHIFT 3
43 #define PGRP_LPMD_SHIFT 4
44 #define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
45 #define PGRP_DRVDN_SHIFT 12
46 #define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
47 #define PGRP_DRVUP_SHIFT 20
48 #define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
49 #define PGRP_SLWR_SHIFT 28
50 #define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
51 #define PGRP_SLWF_SHIFT 30
52 #define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
54 /* Convenient macro for defining pin group properties */
55 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
57 .vddio = PMUX_VDDIO_ ## vdd, \
64 .io = PMUX_PIN_ ## iod, \
67 /* Input and output pins */
68 #define PINI(pg_name, vdd, f0, f1, f2, f3) \
69 PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
70 #define PINO(pg_name, vdd, f0, f1, f2, f3) \
71 PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
73 /* A pin group number which is not used */
74 #define PIN_RESERVED \
75 PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
77 const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
78 /* NAME VDD f0 f1 f2 f3 */
79 PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
80 PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
81 PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
82 PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
83 PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
84 PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
85 PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
86 PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
87 PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
88 PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
89 PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
90 PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
91 PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
92 PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
93 PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
94 PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
95 PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
96 PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
97 PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
98 PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
99 PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
100 PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
101 PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
102 PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
103 PIN_RESERVED, /* Reserved by t114: 0x3060 - 0x3064 */
105 PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
106 PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
107 PIN_RESERVED, /* Reserved by t114: 0x3070 - 0x310c */
147 PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
148 PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
149 PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
150 PIN_RESERVED, /* Reserved by t114: 0x311c - 0x3160 */
168 PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
169 PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
170 PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
171 PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
172 PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
173 PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
174 PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
175 PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
176 PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
177 PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
178 PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
179 PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
180 PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
181 PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
182 PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
183 PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
184 PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
185 PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
186 PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
187 PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
188 PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
189 PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
190 PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
191 PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
192 PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
193 PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
194 PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
195 PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
196 PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
197 PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
198 PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
199 PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
200 PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
201 PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
202 PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
203 PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
204 PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
205 PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
206 PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
207 PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
208 PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
209 PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
210 PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
211 PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
212 PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
213 PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
214 PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
215 PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
216 PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
217 PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
218 PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
219 PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
220 PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
221 PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
222 PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
223 PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
224 PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
225 PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
226 PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
227 PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
228 PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
229 PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
230 PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
231 PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
232 PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
233 PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
234 PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
235 PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
236 PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
237 PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
238 PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
239 PIN_RESERVED, /* Reserved by t114: 0x3280 */
240 PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
241 PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
242 PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
243 PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
244 PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
245 PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
246 PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
247 PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
248 PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
249 PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
250 PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
251 PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
252 PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
253 PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
254 PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
255 PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
256 PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
257 PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
258 PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
259 PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
260 PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
261 PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
262 PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
263 PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
264 PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
265 PIN_RESERVED, /* Reserved by t114: 0x32e8 - 0x32f8 */
270 PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
271 PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
272 PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
273 PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
274 PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
275 PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
276 PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
277 PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
278 PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
279 PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
280 PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
281 PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
282 PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
283 PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
284 PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
285 PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
286 PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
287 PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
288 PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
289 PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
290 PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
291 PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
292 PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
293 PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
294 PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
295 PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
296 PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
297 PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
298 PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
299 PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
300 PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
301 PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
302 PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
303 PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
304 PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
305 PIN_RESERVED, /* Reserved by t114: 0x3388 - 0x338c */
307 PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
308 PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
309 PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
310 PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
311 PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
312 PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
313 PIN_RESERVED, /* Reserved by t114: 0x33a8 - 0x33dc */
327 PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
328 PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
329 PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
330 PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
331 PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
332 PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
333 PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
334 PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
335 PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
336 PIN_RESERVED, /* Reserved by t114: 0x3404 */
337 PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
340 void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
342 struct pmux_tri_ctlr *pmt =
343 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
344 u32 *tri = &pmt->pmt_ctl[pin];
347 /* Error check on pin */
348 assert(pmux_pingrp_isvalid(pin));
352 reg |= PMUX_TRISTATE_MASK;
354 reg &= ~PMUX_TRISTATE_MASK;
358 void pinmux_tristate_enable(enum pmux_pingrp pin)
360 pinmux_set_tristate(pin, 1);
363 void pinmux_tristate_disable(enum pmux_pingrp pin)
365 pinmux_set_tristate(pin, 0);
368 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
370 struct pmux_tri_ctlr *pmt =
371 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
372 u32 *pull = &pmt->pmt_ctl[pin];
375 /* Error check on pin and pupd */
376 assert(pmux_pingrp_isvalid(pin));
377 assert(pmux_pin_pupd_isvalid(pupd));
380 reg &= ~(0x3 << PMUX_PULL_SHIFT);
381 reg |= (pupd << PMUX_PULL_SHIFT);
385 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
387 struct pmux_tri_ctlr *pmt =
388 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
389 u32 *muxctl = &pmt->pmt_ctl[pin];
393 /* Error check on pin and func */
394 assert(pmux_pingrp_isvalid(pin));
395 assert(pmux_func_isvalid(func));
397 if (func & PMUX_FUNC_RSVD1) {
400 /* Search for the appropriate function */
401 for (i = 0; i < 4; i++) {
402 if (tegra_soc_pingroups[pin].funcs[i] == func) {
411 reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
412 reg |= (mux << PMUX_MUXCTL_SHIFT);
417 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
419 struct pmux_tri_ctlr *pmt =
420 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
421 u32 *pin_io = &pmt->pmt_ctl[pin];
424 /* Error check on pin and io */
425 assert(pmux_pingrp_isvalid(pin));
426 assert(pmux_pin_io_isvalid(io));
429 reg &= ~(0x1 << PMUX_IO_SHIFT);
430 reg |= (io & 0x1) << PMUX_IO_SHIFT;
434 static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
436 struct pmux_tri_ctlr *pmt =
437 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
438 u32 *pin_lock = &pmt->pmt_ctl[pin];
441 /* Error check on pin and lock */
442 assert(pmux_pingrp_isvalid(pin));
443 assert(pmux_pin_lock_isvalid(lock));
445 if (lock == PMUX_PIN_LOCK_DEFAULT)
448 reg = readl(pin_lock);
449 reg &= ~(0x1 << PMUX_LOCK_SHIFT);
450 if (lock == PMUX_PIN_LOCK_ENABLE)
451 reg |= (0x1 << PMUX_LOCK_SHIFT);
453 /* lock == DISABLE, which isn't possible */
454 printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
457 writel(reg, pin_lock);
462 static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
464 struct pmux_tri_ctlr *pmt =
465 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
466 u32 *pin_od = &pmt->pmt_ctl[pin];
469 /* Error check on pin and od */
470 assert(pmux_pingrp_isvalid(pin));
471 assert(pmux_pin_od_isvalid(od));
473 if (od == PMUX_PIN_OD_DEFAULT)
477 reg &= ~(0x1 << PMUX_OD_SHIFT);
478 if (od == PMUX_PIN_OD_ENABLE)
479 reg |= (0x1 << PMUX_OD_SHIFT);
485 static int pinmux_set_ioreset(enum pmux_pingrp pin,
486 enum pmux_pin_ioreset ioreset)
488 struct pmux_tri_ctlr *pmt =
489 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
490 u32 *pin_ioreset = &pmt->pmt_ctl[pin];
493 /* Error check on pin and ioreset */
494 assert(pmux_pingrp_isvalid(pin));
495 assert(pmux_pin_ioreset_isvalid(ioreset));
497 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
500 reg = readl(pin_ioreset);
501 reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
502 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
503 reg |= (0x1 << PMUX_IO_RESET_SHIFT);
504 writel(reg, pin_ioreset);
509 static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
510 enum pmux_pin_rcv_sel rcv_sel)
512 struct pmux_tri_ctlr *pmt =
513 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
514 u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
517 /* Error check on pin and rcv_sel */
518 assert(pmux_pingrp_isvalid(pin));
519 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
521 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
524 reg = readl(pin_rcv_sel);
525 reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
526 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
527 reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
528 writel(reg, pin_rcv_sel);
533 void pinmux_config_pingroup(struct pingroup_config *config)
535 enum pmux_pingrp pin = config->pingroup;
537 pinmux_set_func(pin, config->func);
538 pinmux_set_pullupdown(pin, config->pull);
539 pinmux_set_tristate(pin, config->tristate);
540 pinmux_set_io(pin, config->io);
541 pinmux_set_lock(pin, config->lock);
542 pinmux_set_od(pin, config->od);
543 pinmux_set_ioreset(pin, config->ioreset);
544 pinmux_set_rcv_sel(pin, config->rcv_sel);
547 void pinmux_config_table(struct pingroup_config *config, int len)
551 for (i = 0; i < len; i++)
552 pinmux_config_pingroup(&config[i]);
555 static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
557 struct pmux_tri_ctlr *pmt =
558 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
559 u32 *pad_slwf = &pmt->pmt_drive[pad];
562 /* Error check on pad and slwf */
563 assert(pmux_padgrp_isvalid(pad));
564 assert(pmux_pad_slw_isvalid(slwf));
566 /* NONE means unspecified/do not change/use POR value */
567 if (slwf == PGRP_SLWF_NONE)
570 reg = readl(pad_slwf);
571 reg &= ~PGRP_SLWF_MASK;
572 reg |= (slwf << PGRP_SLWF_SHIFT);
573 writel(reg, pad_slwf);
578 static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
580 struct pmux_tri_ctlr *pmt =
581 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
582 u32 *pad_slwr = &pmt->pmt_drive[pad];
585 /* Error check on pad and slwr */
586 assert(pmux_padgrp_isvalid(pad));
587 assert(pmux_pad_slw_isvalid(slwr));
589 /* NONE means unspecified/do not change/use POR value */
590 if (slwr == PGRP_SLWR_NONE)
593 reg = readl(pad_slwr);
594 reg &= ~PGRP_SLWR_MASK;
595 reg |= (slwr << PGRP_SLWR_SHIFT);
596 writel(reg, pad_slwr);
601 static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
603 struct pmux_tri_ctlr *pmt =
604 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
605 u32 *pad_drvup = &pmt->pmt_drive[pad];
608 /* Error check on pad and drvup */
609 assert(pmux_padgrp_isvalid(pad));
610 assert(pmux_pad_drv_isvalid(drvup));
612 /* NONE means unspecified/do not change/use POR value */
613 if (drvup == PGRP_DRVUP_NONE)
616 reg = readl(pad_drvup);
617 reg &= ~PGRP_DRVUP_MASK;
618 reg |= (drvup << PGRP_DRVUP_SHIFT);
619 writel(reg, pad_drvup);
624 static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
626 struct pmux_tri_ctlr *pmt =
627 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
628 u32 *pad_drvdn = &pmt->pmt_drive[pad];
631 /* Error check on pad and drvdn */
632 assert(pmux_padgrp_isvalid(pad));
633 assert(pmux_pad_drv_isvalid(drvdn));
635 /* NONE means unspecified/do not change/use POR value */
636 if (drvdn == PGRP_DRVDN_NONE)
639 reg = readl(pad_drvdn);
640 reg &= ~PGRP_DRVDN_MASK;
641 reg |= (drvdn << PGRP_DRVDN_SHIFT);
642 writel(reg, pad_drvdn);
647 static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
649 struct pmux_tri_ctlr *pmt =
650 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
651 u32 *pad_lpmd = &pmt->pmt_drive[pad];
654 /* Error check pad and lpmd value */
655 assert(pmux_padgrp_isvalid(pad));
656 assert(pmux_pad_lpmd_isvalid(lpmd));
658 /* NONE means unspecified/do not change/use POR value */
659 if (lpmd == PGRP_LPMD_NONE)
662 reg = readl(pad_lpmd);
663 reg &= ~PGRP_LPMD_MASK;
664 reg |= (lpmd << PGRP_LPMD_SHIFT);
665 writel(reg, pad_lpmd);
670 static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
672 struct pmux_tri_ctlr *pmt =
673 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
674 u32 *pad_schmt = &pmt->pmt_drive[pad];
677 /* Error check pad */
678 assert(pmux_padgrp_isvalid(pad));
680 /* NONE means unspecified/do not change/use POR value */
681 if (schmt == PGRP_SCHMT_NONE)
684 reg = readl(pad_schmt);
685 reg &= ~(1 << PGRP_SCHMT_SHIFT);
686 if (schmt == PGRP_SCHMT_ENABLE)
687 reg |= (0x1 << PGRP_SCHMT_SHIFT);
688 writel(reg, pad_schmt);
692 static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
694 struct pmux_tri_ctlr *pmt =
695 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
696 u32 *pad_hsm = &pmt->pmt_drive[pad];
699 /* Error check pad */
700 assert(pmux_padgrp_isvalid(pad));
702 /* NONE means unspecified/do not change/use POR value */
703 if (hsm == PGRP_HSM_NONE)
706 reg = readl(pad_hsm);
707 reg &= ~(1 << PGRP_HSM_SHIFT);
708 if (hsm == PGRP_HSM_ENABLE)
709 reg |= (0x1 << PGRP_HSM_SHIFT);
710 writel(reg, pad_hsm);
715 void padctrl_config_pingroup(struct padctrl_config *config)
717 enum pdrive_pingrp pad = config->padgrp;
719 padgrp_set_drvup_slwf(pad, config->slwf);
720 padgrp_set_drvdn_slwr(pad, config->slwr);
721 padgrp_set_drvup(pad, config->drvup);
722 padgrp_set_drvdn(pad, config->drvdn);
723 padgrp_set_lpmd(pad, config->lpmd);
724 padgrp_set_schmt(pad, config->schmt);
725 padgrp_set_hsm(pad, config->hsm);
728 void padgrp_config_table(struct padctrl_config *config, int len)
732 for (i = 0; i < len; i++)
733 padctrl_config_pingroup(&config[i]);