3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra124 high-level function multiplexing */
11 #include <asm/arch/clock.h>
12 #include <asm/arch/funcmux.h>
13 #include <asm/arch/pinmux.h>
15 int funcmux_select(enum periph_id id, int config)
17 int bad_config = config != FUNCMUX_DEFAULT;
22 case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
23 pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
24 pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
25 pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
26 pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
28 pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
29 pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
30 pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
31 pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
33 pinmux_tristate_disable(PMUX_PINGRP_PJ7);
34 pinmux_tristate_disable(PMUX_PINGRP_PB0);
35 pinmux_tristate_disable(PMUX_PINGRP_PB1);
36 pinmux_tristate_disable(PMUX_PINGRP_PK7);
43 case FUNCMUX_UART1_KBC:
44 pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
46 pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
49 pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
50 pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
52 pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
53 pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
58 /* Add other periph IDs here as needed */
61 debug("%s: invalid periph_id %d", __func__, id);
66 debug("%s: invalid config %d for periph_id %d", __func__,