2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/ap20.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/funcmux.h>
29 #include <asm/arch/pmc.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/arch/tegra20.h>
33 DECLARE_GLOBAL_DATA_PTR;
36 /* UARTs which we can enable */
44 * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
45 * so we are using this value to identify memory size.
48 unsigned int query_sdram_size(void)
50 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
53 reg = readl(&pmc->pmc_scratch20);
54 debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
56 /* bits 31:28 in OdmData are used for RAM size */
57 switch ((reg) >> 28) {
59 return 0x10000000; /* 256 MB */
62 return 0x20000000; /* 512 MB */
64 return 0x40000000; /* 1GB */
70 /* We do not initialise DRAM here. We just query the size */
71 gd->ram_size = query_sdram_size();
75 #ifdef CONFIG_DISPLAY_BOARDINFO
78 printf("Board: %s\n", sysinfo.board_string);
81 #endif /* CONFIG_DISPLAY_BOARDINFO */
83 #ifdef CONFIG_ARCH_CPU_INIT
85 * Note this function is executed by the ARM7TDMI AVP. It does not return
86 * in this case. It is also called once the A9 starts up, but does nothing in
89 int arch_cpu_init(void)
91 /* Fire up the Cortex A9 */
94 /* We didn't do this init in start.S, so do it now */
97 /* Initialize essential common plls */
104 static int uart_configs[] = {
105 #if defined(CONFIG_TEGRA20_UARTA_UAA_UAB)
106 FUNCMUX_UART1_UAA_UAB,
107 #elif defined(CONFIG_TEGRA20_UARTA_GPU)
109 #elif defined(CONFIG_TEGRA20_UARTA_SDIO1)
112 FUNCMUX_UART1_IRRX_IRTX,
121 * Set up the specified uarts
123 * @param uarts_ids Mask containing UARTs to init (UARTx)
125 static void setup_uarts(int uart_ids)
127 static enum periph_id id_for_uart[] = {
135 for (i = 0; i < UART_COUNT; i++) {
136 if (uart_ids & (1 << i)) {
137 enum periph_id id = id_for_uart[i];
139 funcmux_select(id, uart_configs[i]);
140 clock_ll_start_uart(id);
145 void board_init_uart_f(void)
147 int uart_ids = 0; /* bit mask of which UART ids to enable */
149 #ifdef CONFIG_TEGRA20_ENABLE_UARTA
152 #ifdef CONFIG_TEGRA20_ENABLE_UARTB
155 #ifdef CONFIG_TEGRA20_ENABLE_UARTD
158 setup_uarts(uart_ids);
161 #ifndef CONFIG_SYS_DCACHE_OFF
162 void enable_caches(void)
164 /* Enable D-cache. I-cache is already enabled in start.S */