2 * Copyright (c) 2011 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
7 /* Tegra20 Clock control functions */
11 #include <asm/arch/clock.h>
12 #include <asm/arch/tegra.h>
13 #include <asm/arch-tegra/clk_rst.h>
14 #include <asm/arch-tegra/timer.h>
19 * Clock types that we can use as a source. The Tegra20 has muxes for the
20 * peripheral clocks, and in most cases there are four options for the clock
21 * source. This gives us a clock 'type' and exploits what commonality exists
24 * Letters are obvious, except for T which means CLK_M, and S which means the
25 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
26 * datasheet) and PLL_M are different things. The former is the basic
27 * clock supplied to the SOC from an external oscillator. The latter is the
30 * See definitions in clock_id in the header file.
33 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
34 CLOCK_TYPE_MCPA, /* and so on */
38 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
43 CLOCK_TYPE_NONE = -1, /* invalid clock type */
47 CLOCK_MAX_MUX = 4 /* number of source options for each clock */
51 * Clock source mux for each clock type. This just converts our enum into
52 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
53 * is special as it has 5 sources. Since it also has a different number of
54 * bits in its register for the source, we just handle it with a special
57 #define CLK(x) CLOCK_ID_ ## x
58 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
59 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
60 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
61 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
62 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
63 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
64 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
65 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
66 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
70 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
71 * not in the header file since it is for purely internal use - we want
72 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
73 * confusion bewteen PERIPH_ID_... and PERIPHC_...
75 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
78 * Note to SOC vendors: perhaps define a unified numbering for peripherals and
79 * use it for reset, clock enable, clock source/divider and even pinmuxing
82 enum periphc_internal_id {
99 PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
157 * Clock type for each peripheral clock source. We put the name in each
158 * record just so it is easy to match things up
160 #define TYPE(name, type) type
161 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
163 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
164 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
165 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
166 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
167 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
168 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
169 TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
170 TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
173 TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
174 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
175 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
176 TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
177 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
178 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
179 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
180 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
183 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
184 TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
185 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
186 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
187 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
188 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
189 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
190 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
193 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
194 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
195 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
196 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
197 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
198 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
199 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
200 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
203 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
204 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
205 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
206 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
207 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
208 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
209 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
210 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
213 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
214 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
215 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
216 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
217 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
218 TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
219 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
220 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
223 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
224 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
225 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
226 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
227 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
228 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
232 * This array translates a periph_id to a periphc_internal_id
234 * Not present/matched up:
235 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
236 * SPDIF - which is both 0x08 and 0x0c
239 #define NONE(name) (-1)
240 #define OFFSET(name, value) PERIPHC_ ## name
241 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
250 PERIPHC_UART2, /* and vfir 0x68 */
255 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
282 /* Middle word: 63:32 */
294 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
304 PERIPHC_TVO, /* also CVE 0x40 */
322 /* Upper word 95:64 */
357 * Get the oscillator frequency, from the corresponding hardware configuration
358 * field. T20 has 4 frequencies that it supports.
360 enum clock_osc_freq clock_get_osc_freq(void)
362 struct clk_rst_ctlr *clkrst =
363 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
366 reg = readl(&clkrst->crc_osc_ctrl);
367 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
370 /* Returns a pointer to the clock source register for a peripheral */
371 u32 *get_periph_source_reg(enum periph_id periph_id)
373 struct clk_rst_ctlr *clkrst =
374 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
375 enum periphc_internal_id internal_id;
377 assert(clock_periph_id_isvalid(periph_id));
378 internal_id = periph_id_to_internal_id[periph_id];
379 assert(internal_id != -1);
380 return &clkrst->crc_clk_src[internal_id];
384 * Given a peripheral ID and the required source clock, this returns which
385 * value should be programmed into the source mux for that peripheral.
387 * There is special code here to handle the one source type with 5 sources.
389 * @param periph_id peripheral to start
390 * @param source PLL id of required parent clock
391 * @param mux_bits Set to number of bits in mux register: 2 or 4
392 * @param divider_bits Set to number of divider bits (8 or 16)
393 * @return mux value (0-4, or -1 if not found)
395 int get_periph_clock_source(enum periph_id periph_id,
396 enum clock_id parent, int *mux_bits, int *divider_bits)
398 enum clock_type_id type;
399 enum periphc_internal_id internal_id;
402 assert(clock_periph_id_isvalid(periph_id));
404 internal_id = periph_id_to_internal_id[periph_id];
405 assert(periphc_internal_id_isvalid(internal_id));
407 type = clock_periph_type[internal_id];
408 assert(clock_type_id_isvalid(type));
411 * Special cases here for the clock with a 4-bit source mux and I2C
412 * with its 16-bit divisor
414 if (type == CLOCK_TYPE_PCXTS)
415 *mux_bits = MASK_BITS_31_28;
417 *mux_bits = MASK_BITS_31_30;
418 if (type == CLOCK_TYPE_PCMT16)
423 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
424 if (clock_source[type][mux] == parent)
428 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
429 * which is not in our table. If not, then they are asking for a
430 * source which this peripheral can't access through its mux.
432 assert(type == CLOCK_TYPE_PCXTS);
433 assert(parent == CLOCK_ID_SFROM32KHZ);
434 if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
435 return 4; /* mux value for this clock */
437 /* if we get here, either us or the caller has made a mistake */
438 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
443 void clock_set_enable(enum periph_id periph_id, int enable)
445 struct clk_rst_ctlr *clkrst =
446 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
447 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
450 /* Enable/disable the clock to this peripheral */
451 assert(clock_periph_id_isvalid(periph_id));
454 reg |= PERIPH_MASK(periph_id);
456 reg &= ~PERIPH_MASK(periph_id);
460 void reset_set_enable(enum periph_id periph_id, int enable)
462 struct clk_rst_ctlr *clkrst =
463 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
464 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
467 /* Enable/disable reset to the peripheral */
468 assert(clock_periph_id_isvalid(periph_id));
471 reg |= PERIPH_MASK(periph_id);
473 reg &= ~PERIPH_MASK(periph_id);
477 #ifdef CONFIG_OF_CONTROL
479 * Convert a device tree clock ID to our peripheral ID. They are mostly
480 * the same but we are very cautious so we check that a valid clock ID is
483 * @param clk_id Clock ID according to tegra20 device tree binding
484 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
486 enum periph_id clk_id_to_periph_id(int clk_id)
488 if (clk_id > PERIPH_ID_COUNT)
489 return PERIPH_ID_NONE;
492 case PERIPH_ID_RESERVED1:
493 case PERIPH_ID_RESERVED2:
494 case PERIPH_ID_RESERVED30:
495 case PERIPH_ID_RESERVED35:
496 case PERIPH_ID_RESERVED56:
497 case PERIPH_ID_RESERVED74:
498 case PERIPH_ID_RESERVED76:
499 case PERIPH_ID_RESERVED77:
500 case PERIPH_ID_RESERVED78:
501 case PERIPH_ID_RESERVED79:
502 case PERIPH_ID_RESERVED80:
503 case PERIPH_ID_RESERVED81:
504 case PERIPH_ID_RESERVED82:
505 case PERIPH_ID_RESERVED83:
506 case PERIPH_ID_RESERVED91:
507 return PERIPH_ID_NONE;
512 #endif /* CONFIG_OF_CONTROL */
514 void clock_early_init(void)
517 * PLLP output frequency set to 216MHz
518 * PLLC output frequency set to 600Mhz
520 * TODO: Can we calculate these values instead of hard-coding?
522 switch (clock_get_osc_freq()) {
523 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
524 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
525 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
528 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
529 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
530 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
533 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
534 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
535 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
537 case CLOCK_OSC_FREQ_19_2:
540 * These are not supported. It is too early to print a
541 * message and the UART likely won't work anyway due to the
542 * oscillator being wrong.
548 void arch_timer_init(void)