2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 /* Tegra20 Clock control functions */
26 #include <asm/arch/clock.h>
27 #include <asm/arch/tegra.h>
28 #include <asm/arch-tegra/clk_rst.h>
29 #include <asm/arch-tegra/timer.h>
34 * This is our record of the current clock rate of each clock. We don't
35 * fill all of these in since we are only really interested in clocks which
38 static unsigned pll_rate[CLOCK_ID_COUNT];
41 * The oscillator frequency is fixed to one of four set values. Based on this
42 * the other clocks are set up appropriately.
44 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
52 * Clock types that we can use as a source. The Tegra20 has muxes for the
53 * peripheral clocks, and in most cases there are four options for the clock
54 * source. This gives us a clock 'type' and exploits what commonality exists
57 * Letters are obvious, except for T which means CLK_M, and S which means the
58 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
59 * datasheet) and PLL_M are different things. The former is the basic
60 * clock supplied to the SOC from an external oscillator. The latter is the
63 * See definitions in clock_id in the header file.
66 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
67 CLOCK_TYPE_MCPA, /* and so on */
71 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
76 CLOCK_TYPE_NONE = -1, /* invalid clock type */
79 /* return 1 if a peripheral ID is in range */
80 #define clock_type_id_isvalid(id) ((id) >= 0 && \
81 (id) < CLOCK_TYPE_COUNT)
83 char pllp_valid = 1; /* PLLP is set up correctly */
86 CLOCK_MAX_MUX = 4 /* number of source options for each clock */
90 * Clock source mux for each clock type. This just converts our enum into
91 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
92 * is special as it has 5 sources. Since it also has a different number of
93 * bits in its register for the source, we just handle it with a special
96 #define CLK(x) CLOCK_ID_ ## x
97 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
98 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
99 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
100 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
101 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
102 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
103 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
104 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
105 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
109 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
110 * not in the header file since it is for purely internal use - we want
111 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
112 * confusion bewteen PERIPH_ID_... and PERIPHC_...
114 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
117 * Note to SOC vendors: perhaps define a unified numbering for peripherals and
118 * use it for reset, clock enable, clock source/divider and even pinmuxing
121 enum periphc_internal_id {
138 PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
195 /* return 1 if a periphc_internal_id is in range */
196 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
197 (id) < PERIPHC_COUNT)
200 * Clock type for each peripheral clock source. We put the name in each
201 * record just so it is easy to match things up
203 #define TYPE(name, type) type
204 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
206 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
207 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
208 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
209 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
210 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
211 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
212 TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
213 TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
216 TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
217 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
218 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
219 TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
220 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
221 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
222 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
223 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
226 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
227 TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
228 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
229 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
230 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
231 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
232 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
233 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
236 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
237 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
238 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
239 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
240 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
241 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
242 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
243 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
246 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
247 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
248 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
249 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
250 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
251 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
252 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
253 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
256 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
257 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
258 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
259 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
260 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
261 TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
262 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
263 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
266 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
267 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
268 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
269 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
270 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
271 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
275 * This array translates a periph_id to a periphc_internal_id
277 * Not present/matched up:
278 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
279 * SPDIF - which is both 0x08 and 0x0c
282 #define NONE(name) (-1)
283 #define OFFSET(name, value) PERIPHC_ ## name
284 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
293 PERIPHC_UART2, /* and vfir 0x68 */
298 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
325 /* Middle word: 63:32 */
337 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
347 PERIPHC_TVO, /* also CVE 0x40 */
365 /* Upper word 95:64 */
399 /* number of clock outputs of a PLL */
400 static const u8 pll_num_clkouts[] = {
410 * Get the oscillator frequency, from the corresponding hardware configuration
413 enum clock_osc_freq clock_get_osc_freq(void)
415 struct clk_rst_ctlr *clkrst =
416 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
419 reg = readl(&clkrst->crc_osc_ctrl);
420 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
423 int clock_get_osc_bypass(void)
425 struct clk_rst_ctlr *clkrst =
426 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
429 reg = readl(&clkrst->crc_osc_ctrl);
430 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
433 /* Returns a pointer to the registers of the given pll */
434 static struct clk_pll *get_pll(enum clock_id clkid)
436 struct clk_rst_ctlr *clkrst =
437 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
439 assert(clock_id_is_pll(clkid));
440 return &clkrst->crc_pll[clkid];
443 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
444 u32 *divp, u32 *cpcon, u32 *lfcon)
446 struct clk_pll *pll = get_pll(clkid);
449 assert(clkid != CLOCK_ID_USB);
451 /* Safety check, adds to code size but is small */
452 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
454 data = readl(&pll->pll_base);
455 *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
456 *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
457 *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
458 data = readl(&pll->pll_misc);
459 *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
460 *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
465 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
466 u32 divp, u32 cpcon, u32 lfcon)
468 struct clk_pll *pll = get_pll(clkid);
472 * We cheat by treating all PLL (except PLLU) in the same fashion.
473 * This works only because:
474 * - same fields are always mapped at same offsets, except DCCON
475 * - DCCON is always 0, doesn't conflict
476 * - M,N, P of PLLP values are ignored for PLLP
478 data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
479 writel(data, &pll->pll_misc);
481 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
482 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
484 if (clkid == CLOCK_ID_USB)
485 data |= divp << PLLU_VCO_FREQ_SHIFT;
487 data |= divp << PLL_DIVP_SHIFT;
488 writel(data, &pll->pll_base);
490 /* calculate the stable time */
491 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
494 /* return 1 if a peripheral ID is in range and valid */
495 static int clock_periph_id_isvalid(enum periph_id id)
497 if (id < PERIPH_ID_FIRST || id >= PERIPH_ID_COUNT)
498 printf("Peripheral id %d out of range\n", id);
501 case PERIPH_ID_RESERVED1:
502 case PERIPH_ID_RESERVED2:
503 case PERIPH_ID_RESERVED30:
504 case PERIPH_ID_RESERVED35:
505 case PERIPH_ID_RESERVED56:
506 case PERIPH_ID_RESERVED74:
507 case PERIPH_ID_RESERVED76:
508 case PERIPH_ID_RESERVED77:
509 case PERIPH_ID_RESERVED78:
510 case PERIPH_ID_RESERVED79:
511 case PERIPH_ID_RESERVED80:
512 case PERIPH_ID_RESERVED81:
513 case PERIPH_ID_RESERVED82:
514 case PERIPH_ID_RESERVED83:
515 case PERIPH_ID_RESERVED91:
516 printf("Peripheral id %d is reserved\n", id);
525 /* Returns a pointer to the clock source register for a peripheral */
526 static u32 *get_periph_source_reg(enum periph_id periph_id)
528 struct clk_rst_ctlr *clkrst =
529 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
530 enum periphc_internal_id internal_id;
532 assert(clock_periph_id_isvalid(periph_id));
533 internal_id = periph_id_to_internal_id[periph_id];
534 assert(internal_id != -1);
535 return &clkrst->crc_clk_src[internal_id];
538 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
541 u32 *reg = get_periph_source_reg(periph_id);
546 value &= ~OUT_CLK_SOURCE_MASK;
547 value |= source << OUT_CLK_SOURCE_SHIFT;
549 value &= ~OUT_CLK_DIVISOR_MASK;
550 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
555 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
557 u32 *reg = get_periph_source_reg(periph_id);
559 clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
560 source << OUT_CLK_SOURCE_SHIFT);
564 * Given the parent's rate and the required rate for the children, this works
565 * out the peripheral clock divider to use, in 7.1 binary format.
567 * @param divider_bits number of divider bits (8 or 16)
568 * @param parent_rate clock rate of parent clock in Hz
569 * @param rate required clock rate for this clock
570 * @return divider which should be used
572 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
575 u64 divider = parent_rate * 2;
576 unsigned max_divider = 1 << divider_bits;
579 do_div(divider, rate);
581 if ((s64)divider - 2 < 0)
584 if ((s64)divider - 2 >= max_divider)
591 * Given the parent's rate and the divider in 7.1 format, this works out the
592 * resulting peripheral clock rate.
594 * @param parent_rate clock rate of parent clock in Hz
595 * @param divider which should be used in 7.1 format
596 * @return effective clock rate of peripheral
598 static unsigned long get_rate_from_divider(unsigned long parent_rate,
603 rate = (u64)parent_rate * 2;
604 do_div(rate, divider + 2);
608 unsigned long clock_get_periph_rate(enum periph_id periph_id,
609 enum clock_id parent)
611 u32 *reg = get_periph_source_reg(periph_id);
613 return get_rate_from_divider(pll_rate[parent],
614 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
617 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
619 struct clk_pll *pll = get_pll(clkid);
620 int data = 0, div = 0, offset = 0;
622 if (!clock_id_is_pll(clkid))
625 if (pllout + 1 > pll_num_clkouts[clkid])
628 div = clk_get_divider(8, pll_rate[clkid], rate);
633 /* out2 and out4 are in the high part of the register */
634 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
637 data = (div << PLL_OUT_RATIO_SHIFT) |
638 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
639 clrsetbits_le32(&pll->pll_out[pllout >> 1],
640 PLL_OUT_RATIO_MASK << offset, data << offset);
646 * Find the best available 7.1 format divisor given a parent clock rate and
647 * required child clock rate. This function assumes that a second-stage
648 * divisor is available which can divide by powers of 2 from 1 to 256.
650 * @param divider_bits number of divider bits (8 or 16)
651 * @param parent_rate clock rate of parent clock in Hz
652 * @param rate required clock rate for this clock
653 * @param extra_div value for the second-stage divisor (not set if this
654 * function returns -1.
655 * @return divider which should be used, or -1 if nothing is valid
658 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
659 unsigned long rate, int *extra_div)
662 int best_divider = -1;
663 int best_error = rate;
665 /* try dividers from 1 to 256 and find closest match */
666 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
667 unsigned divided_parent = parent_rate >> shift;
668 int divider = clk_get_divider(divider_bits, divided_parent,
670 unsigned effective_rate = get_rate_from_divider(divided_parent,
672 int error = rate - effective_rate;
674 /* Given a valid divider, look for the lowest error */
675 if (divider != -1 && error < best_error) {
677 *extra_div = 1 << shift;
678 best_divider = divider;
682 /* return what we found - *extra_div will already be set */
687 * Given a peripheral ID and the required source clock, this returns which
688 * value should be programmed into the source mux for that peripheral.
690 * There is special code here to handle the one source type with 5 sources.
692 * @param periph_id peripheral to start
693 * @param source PLL id of required parent clock
694 * @param mux_bits Set to number of bits in mux register: 2 or 4
695 * @param divider_bits Set to number of divider bits (8 or 16)
696 * @return mux value (0-4, or -1 if not found)
698 static int get_periph_clock_source(enum periph_id periph_id,
699 enum clock_id parent, int *mux_bits, int *divider_bits)
701 enum clock_type_id type;
702 enum periphc_internal_id internal_id;
705 assert(clock_periph_id_isvalid(periph_id));
707 internal_id = periph_id_to_internal_id[periph_id];
708 assert(periphc_internal_id_isvalid(internal_id));
710 type = clock_periph_type[internal_id];
711 assert(clock_type_id_isvalid(type));
714 * Special cases here for the clock with a 4-bit source mux and I2C
715 * with its 16-bit divisor
717 if (type == CLOCK_TYPE_PCXTS)
721 if (type == CLOCK_TYPE_PCMT16)
726 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
727 if (clock_source[type][mux] == parent)
731 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
732 * which is not in our table. If not, then they are asking for a
733 * source which this peripheral can't access through its mux.
735 assert(type == CLOCK_TYPE_PCXTS);
736 assert(parent == CLOCK_ID_SFROM32KHZ);
737 if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
738 return 4; /* mux value for this clock */
740 /* if we get here, either us or the caller has made a mistake */
741 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
747 * Adjust peripheral PLL to use the given divider and source.
749 * @param periph_id peripheral to adjust
750 * @param source Source number (0-3 or 0-7)
751 * @param mux_bits Number of mux bits (2 or 4)
752 * @param divider Required divider in 7.1 or 15.1 format
753 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
754 * for this peripheral)
756 static int adjust_periph_pll(enum periph_id periph_id, int source,
757 int mux_bits, unsigned divider)
759 u32 *reg = get_periph_source_reg(periph_id);
761 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
762 divider << OUT_CLK_DIVISOR_SHIFT);
765 /* work out the source clock and set it */
769 clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
770 source << OUT_CLK_SOURCE4_SHIFT);
772 clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
773 source << OUT_CLK_SOURCE_SHIFT);
779 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
780 enum clock_id parent, unsigned rate, int *extra_div)
782 unsigned effective_rate;
783 int mux_bits, divider_bits, source;
786 /* work out the source clock and set it */
787 source = get_periph_clock_source(periph_id, parent, &mux_bits,
791 divider = find_best_divider(divider_bits, pll_rate[parent],
794 divider = clk_get_divider(divider_bits, pll_rate[parent],
796 assert(divider >= 0);
797 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
799 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
800 get_periph_source_reg(periph_id),
801 readl(get_periph_source_reg(periph_id)));
803 /* Check what we ended up with. This shouldn't matter though */
804 effective_rate = clock_get_periph_rate(periph_id, parent);
806 effective_rate /= *extra_div;
807 if (rate != effective_rate)
808 debug("Requested clock rate %u not honored (got %u)\n",
809 rate, effective_rate);
810 return effective_rate;
813 unsigned clock_start_periph_pll(enum periph_id periph_id,
814 enum clock_id parent, unsigned rate)
816 unsigned effective_rate;
818 reset_set_enable(periph_id, 1);
819 clock_enable(periph_id);
821 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
824 reset_set_enable(periph_id, 0);
825 return effective_rate;
828 void clock_set_enable(enum periph_id periph_id, int enable)
830 struct clk_rst_ctlr *clkrst =
831 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
832 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
835 /* Enable/disable the clock to this peripheral */
836 assert(clock_periph_id_isvalid(periph_id));
839 reg |= PERIPH_MASK(periph_id);
841 reg &= ~PERIPH_MASK(periph_id);
845 void clock_enable(enum periph_id clkid)
847 clock_set_enable(clkid, 1);
850 void clock_disable(enum periph_id clkid)
852 clock_set_enable(clkid, 0);
855 void reset_set_enable(enum periph_id periph_id, int enable)
857 struct clk_rst_ctlr *clkrst =
858 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
859 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
862 /* Enable/disable reset to the peripheral */
863 assert(clock_periph_id_isvalid(periph_id));
866 reg |= PERIPH_MASK(periph_id);
868 reg &= ~PERIPH_MASK(periph_id);
872 void reset_periph(enum periph_id periph_id, int us_delay)
874 /* Put peripheral into reset */
875 reset_set_enable(periph_id, 1);
879 reset_set_enable(periph_id, 0);
884 void reset_cmplx_set_enable(int cpu, int which, int reset)
886 struct clk_rst_ctlr *clkrst =
887 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
890 /* Form the mask, which depends on the cpu chosen. Tegra20 has 2 */
891 assert(cpu >= 0 && cpu < 2);
894 /* either enable or disable those reset for that CPU */
896 writel(mask, &clkrst->crc_cpu_cmplx_set);
898 writel(mask, &clkrst->crc_cpu_cmplx_clr);
901 unsigned clock_get_rate(enum clock_id clkid)
909 parent_rate = osc_freq[clock_get_osc_freq()];
910 if (clkid == CLOCK_ID_OSC)
913 pll = get_pll(clkid);
914 base = readl(&pll->pll_base);
916 /* Oh for bf_unpack()... */
917 rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
918 divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
919 if (clkid == CLOCK_ID_USB)
920 divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
922 divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
928 * Set the output frequency you want for each PLL clock.
929 * PLL output frequencies are programmed by setting their N, M and P values.
930 * The governing equations are:
931 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
932 * where Fo is the output frequency from the PLL.
933 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
934 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
935 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
937 * @param n PLL feedback divider(DIVN)
938 * @param m PLL input divider(DIVN)
939 * @param p post divider(DIVP)
940 * @param cpcon base PLL charge pump(CPCON)
941 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
942 * be overriden), 1 if PLL is already correct
944 static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
950 pll = get_pll(clkid);
952 base_reg = readl(&pll->pll_base);
954 /* Set BYPASS, m, n and p to PLL_BASE */
955 base_reg &= ~PLL_DIVM_MASK;
956 base_reg |= m << PLL_DIVM_SHIFT;
958 base_reg &= ~PLL_DIVN_MASK;
959 base_reg |= n << PLL_DIVN_SHIFT;
961 base_reg &= ~PLL_DIVP_MASK;
962 base_reg |= p << PLL_DIVP_SHIFT;
964 if (clkid == CLOCK_ID_PERIPH) {
966 * If the PLL is already set up, check that it is correct
967 * and record this info for clock_verify() to check.
969 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
970 base_reg |= PLL_ENABLE_MASK;
971 if (base_reg != readl(&pll->pll_base))
973 return pllp_valid ? 1 : -1;
975 base_reg |= PLL_BASE_OVRRIDE_MASK;
978 base_reg |= PLL_BYPASS_MASK;
979 writel(base_reg, &pll->pll_base);
981 /* Set cpcon to PLL_MISC */
982 misc_reg = readl(&pll->pll_misc);
983 misc_reg &= ~PLL_CPCON_MASK;
984 misc_reg |= cpcon << PLL_CPCON_SHIFT;
985 writel(misc_reg, &pll->pll_misc);
988 base_reg |= PLL_ENABLE_MASK;
989 writel(base_reg, &pll->pll_base);
992 base_reg &= ~PLL_BYPASS_MASK;
993 writel(base_reg, &pll->pll_base);
998 void clock_ll_start_uart(enum periph_id periph_id)
1000 /* Assert UART reset and enable clock */
1001 reset_set_enable(periph_id, 1);
1002 clock_enable(periph_id);
1003 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
1008 /* De-assert reset to UART */
1009 reset_set_enable(periph_id, 0);
1012 #ifdef CONFIG_OF_CONTROL
1014 * Convert a device tree clock ID to our peripheral ID. They are mostly
1015 * the same but we are very cautious so we check that a valid clock ID is
1018 * @param clk_id Clock ID according to tegra20 device tree binding
1019 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
1021 static enum periph_id clk_id_to_periph_id(int clk_id)
1024 return PERIPH_ID_NONE;
1047 return PERIPH_ID_NONE;
1053 int clock_decode_periph_id(const void *blob, int node)
1059 err = fdtdec_get_int_array(blob, node, "clocks", cell,
1063 id = clk_id_to_periph_id(cell[1]);
1064 assert(clock_periph_id_isvalid(id));
1067 #endif /* CONFIG_OF_CONTROL */
1069 int clock_verify(void)
1071 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
1072 u32 reg = readl(&pll->pll_base);
1075 printf("Warning: PLLP %x is not correct\n", reg);
1078 debug("PLLX %x is correct\n", reg);
1082 void clock_early_init(void)
1085 * PLLP output frequency set to 216MHz
1086 * PLLC output frequency set to 600Mhz
1088 * TODO: Can we calculate these values instead of hard-coding?
1090 switch (clock_get_osc_freq()) {
1091 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
1092 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
1093 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
1096 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
1097 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
1098 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
1101 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
1102 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
1103 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
1105 case CLOCK_OSC_FREQ_19_2:
1108 * These are not supported. It is too early to print a
1109 * message and the UART likely won't work anyway due to the
1110 * oscillator being wrong.
1116 void clock_init(void)
1118 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
1119 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
1120 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
1121 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
1122 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
1123 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
1124 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
1125 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);