2 * Copyright (c) 2011 The Chromium OS Authors.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/ap20.h>
27 #include <asm/arch/apb_misc.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/emc.h>
30 #include <asm/arch/tegra20.h>
33 * The EMC registers have shadow registers. When the EMC clock is updated
34 * in the clock controller, the shadow registers are copied to the active
35 * registers, allowing glitchless memory bus frequency changes.
36 * This function updates the shadow registers for a new clock frequency,
37 * and relies on the clock lock on the emc clock to avoid races between
38 * multiple frequency changes
42 * This table defines the ordering of the registers provided to
44 * TODO: Convert to fdt version once available
46 static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
65 0x74, /* BURST_REFRESH_NUM */
76 0xa0, /* TCLKSTABLE */
79 0xac, /* QUSE_EXTRA */
80 0x114, /* FBIO_CFG6 */
83 0x104, /* FBIO_CFG5 */
84 0x2bc, /* CFG_DIG_DLL */
85 0x2c0, /* DLL_XFORM_DQS */
86 0x2c4, /* DLL_XFORM_QUSE */
87 0x2e0, /* ZCAL_REF_CNT */
88 0x2e4, /* ZCAL_WAIT_CNT */
89 0x2a8, /* AUTO_CAL_INTERVAL */
90 0x2d0, /* CFG_CLKTRIM_0 */
91 0x2d4, /* CFG_CLKTRIM_1 */
92 0x2d8, /* CFG_CLKTRIM_2 */
95 struct emc_ctlr *emc_get_controller(const void *blob)
100 node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
102 addr = fdtdec_get_addr(blob, node, "reg");
103 if (addr != FDT_ADDR_T_NONE)
104 return (struct emc_ctlr *)addr;
109 /* Error codes we use */
111 ERR_NO_EMC_NODE = -10,
117 ERR_RAM_CODE_NOT_FOUND,
121 * Find EMC tables for the given ram code.
123 * The tegra EMC binding has two options, one using the ram code and one not.
124 * We detect which is in use by looking for the nvidia,use-ram-code property.
125 * If this is not present, then the EMC tables are directly below 'node',
126 * otherwise we select the correct emc-tables subnode based on the 'ram_code'
129 * @param blob Device tree blob
130 * @param node EMC node (nvidia,tegra20-emc compatible string)
131 * @param ram_code RAM code to select (0-3, or -1 if unknown)
132 * @return 0 if ok, otherwise a -ve ERR_ code (see enum above)
134 static int find_emc_tables(const void *blob, int node, int ram_code)
140 /* If we are using RAM codes, scan through the tables for our code */
141 need_ram_code = fdtdec_get_bool(blob, node, "nvidia,use-ram-code");
144 if (ram_code == -1) {
145 debug("%s: RAM code required but not supplied\n", __func__);
146 return ERR_NO_RAM_CODE;
153 * Sadly there is no compatible string so we cannot use
154 * fdtdec_next_compatible_subnode().
156 offset = fdt_next_node(blob, offset, &depth);
160 /* Make sure this is a direct subnode */
163 if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL)))
166 if (fdtdec_get_int(blob, offset, "nvidia,ram-code", -1)
171 debug("%s: Could not find tables for RAM code %d\n", __func__,
173 return ERR_RAM_CODE_NOT_FOUND;
177 * Decode the EMC node of the device tree, returning a pointer to the emc
178 * controller and the table to be used for the given rate.
180 * @param blob Device tree blob
181 * @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
182 * @param emcp Returns address of EMC controller registers
183 * @param tablep Returns pointer to table to program into EMC. There are
184 * TEGRA_EMC_NUM_REGS entries, destined for offsets as per the
185 * emc_reg_addr array.
186 * @return 0 if ok, otherwise a -ve error code which will allow someone to
187 * figure out roughly what went wrong by looking at this code.
189 static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
192 struct apb_misc_pp_ctlr *pp =
193 (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
198 ram_code = (readl(&pp->strapping_opt_a) & RAM_CODE_MASK)
201 * The EMC clock rate is twice the bus rate, and the bus rate is
204 rate = rate / 2 / 1000;
206 node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
208 debug("%s: No EMC node found in FDT\n", __func__);
209 return ERR_NO_EMC_NODE;
211 *emcp = (struct emc_ctlr *)fdtdec_get_addr(blob, node, "reg");
212 if (*emcp == (struct emc_ctlr *)FDT_ADDR_T_NONE) {
213 debug("%s: No EMC node reg property\n", __func__);
214 return ERR_NO_EMC_REG;
217 /* Work out the parent node which contains our EMC tables */
218 node = find_emc_tables(blob, node, ram_code & 3);
226 node = fdtdec_next_compatible_subnode(blob, node,
227 COMPAT_NVIDIA_TEGRA20_EMC_TABLE, &depth);
230 node_rate = fdtdec_get_int(blob, node, "clock-frequency", -1);
231 if (node_rate == -1) {
232 debug("%s: Missing clock-frequency\n", __func__);
233 return ERR_NO_FREQ; /* we expect this property */
236 if (node_rate == rate)
240 debug("%s: No node found for clock frequency %d\n", __func__,
242 return ERR_FREQ_NOT_FOUND;
245 *tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers",
248 debug("%s: node '%s' array missing / wrong size\n", __func__,
249 fdt_get_name(blob, node, NULL));
257 int tegra_set_emc(const void *blob, unsigned rate)
259 struct emc_ctlr *emc;
263 err = decode_emc(blob, rate, &emc, &table);
265 debug("Warning: no valid EMC (%d), memory timings unset\n",
270 debug("%s: Table found, setting EMC values as follows:\n", __func__);
271 for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) {
272 u32 value = fdt32_to_cpu(table[i]);
273 u32 addr = (uintptr_t)emc + emc_reg_addr[i];
275 debug(" %#x: %#x\n", addr, value);
279 /* trigger emc with new settings */
280 clock_adjust_periph_pll_div(PERIPH_ID_EMC, CLOCK_ID_MEMORY,
281 clock_get_rate(CLOCK_ID_MEMORY), NULL);
282 debug("EMC clock set to %lu\n",
283 clock_get_periph_rate(PERIPH_ID_EMC, CLOCK_ID_MEMORY));