2 * Copyright (c) 2011 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
7 /* Tegra20 pin multiplexing functions */
11 #include <asm/arch/tegra.h>
12 #include <asm/arch/pinmux.h>
16 * This defines the order of the pin mux control bits in the registers. For
17 * some reason there is no correspendence between the tristate, pin mux and
18 * pullup/pulldown registers.
21 /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
40 /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
59 /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
78 /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
97 /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
116 /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
135 /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
158 * And this defines the order of the pullup/pulldown controls which are again
159 * in a different order
162 /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
181 /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
199 /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
218 /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
237 /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
259 struct tegra_pingroup_desc {
261 enum pmux_func funcs[4];
262 enum pmux_vddio vddio;
263 enum pmux_ctlid ctl_id;
264 enum pmux_pullid pull_id;
268 /* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
269 #define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
271 /* Mask value for a tristate (within TRISTATE_REG(id)) */
272 #define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
274 /* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
275 #define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
277 /* Converts a PUCTL id to a shift position */
278 #define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
280 /* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
281 #define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
283 /* Converts a MUXCTL id to a shift position */
284 #define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
286 /* Convenient macro for defining pin group properties */
287 #define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
289 .vddio = PMUX_VDDIO_ ## vdd, \
300 /* A normal pin group where the mux name and pull-up name match */
301 #define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
302 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
303 MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
305 /* A pin group where the pull-up name doesn't have a 1-1 mapping */
306 #define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
307 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
308 MUXCTL_ ## pg_name, PUCTL_ ## pupd)
310 /* A pin group number which is not used */
311 #define PIN_RESERVED \
312 PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
314 const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
315 PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
316 PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
317 PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
318 PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
319 PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
320 PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
321 PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
323 PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
325 PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
326 PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
327 PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
328 PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
329 PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
330 PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
331 PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
332 PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
334 PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
336 PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
337 PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
338 PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
339 PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
340 PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
341 PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
342 PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
344 PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
345 PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
346 PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
347 PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
348 PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
349 PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
350 PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
351 PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
353 PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
354 PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
355 PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
357 PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
358 PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
359 PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
360 PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
362 PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
363 PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
364 PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
365 PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
366 PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
367 PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
368 PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
369 PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
371 PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
372 PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
373 PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
374 PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
375 PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
376 PIN(UAD, UART, UARTB, SPDIF, UARTA, SPI4, SPDIF),
377 PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
378 PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
381 PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
382 PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
385 PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
386 PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
387 PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
390 PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
391 PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
392 PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
393 PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
394 PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
395 PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
396 PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
397 PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
399 PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
400 PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
401 PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
402 PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
403 PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
404 PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
405 PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
406 PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
408 PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
409 PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
410 PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
411 PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
412 PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
413 PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
414 PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
415 PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
417 PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
418 PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
419 PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
420 PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
421 PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
422 PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
423 PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
424 PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
427 PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
428 PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
429 PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
430 PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
431 PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
432 PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
433 PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
434 PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
436 PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
438 PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
439 PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
440 PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
441 PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
442 PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
443 PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
445 /* these pin groups only have pullup and pull down control */
446 PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
448 PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
450 PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
452 PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
454 PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
456 PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
458 PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
460 PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
462 PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
466 void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
468 struct pmux_tri_ctlr *pmt =
469 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
470 u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
475 reg |= TRISTATE_MASK(pin);
477 reg &= ~TRISTATE_MASK(pin);
481 void pinmux_tristate_enable(enum pmux_pingrp pin)
483 pinmux_set_tristate(pin, 1);
486 void pinmux_tristate_disable(enum pmux_pingrp pin)
488 pinmux_set_tristate(pin, 0);
491 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
493 struct pmux_tri_ctlr *pmt =
494 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
495 enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id;
496 u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)];
499 mask_bit = PULL_SHIFT(pull_id);
502 reg &= ~(0x3 << mask_bit);
503 reg |= pupd << mask_bit;
507 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
509 struct pmux_tri_ctlr *pmt =
510 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
511 enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id;
512 u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)];
517 assert(pmux_func_isvalid(func));
519 /* Handle special values */
520 if (func >= PMUX_FUNC_RSVD1) {
521 mux = (func - PMUX_FUNC_RSVD1) & 0x3;
523 /* Search for the appropriate function */
524 for (i = 0; i < 4; i++) {
525 if (tegra_soc_pingroups[pin].funcs[i] == func) {
533 mask_bit = MUXCTL_SHIFT(mux_id);
535 reg &= ~(0x3 << mask_bit);
536 reg |= mux << mask_bit;
540 void pinmux_config_pingroup(const struct pingroup_config *config)
542 enum pmux_pingrp pin = config->pingroup;
544 pinmux_set_func(pin, config->func);
545 pinmux_set_pullupdown(pin, config->pull);
546 pinmux_set_tristate(pin, config->tristate);
549 void pinmux_config_table(const struct pingroup_config *config, int len)
553 for (i = 0; i < len; i++)
554 pinmux_config_pingroup(&config[i]);