2 * (C) Copyright 2010 - 2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/ap20.h>
27 #include <asm/arch/clk_rst.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/flow.h>
30 #include <asm/arch/pinmux.h>
31 #include <asm/arch/pmc.h>
32 #include <asm/arch/tegra20.h>
33 #include <asm/arch/warmboot.h>
34 #include "warmboot_avp.h"
36 #define DEBUG_RESET_CORESIGHT
40 struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
41 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
42 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
43 struct clk_rst_ctlr *clkrst =
44 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
45 union osc_ctrl_reg osc_ctrl;
46 union pllx_base_reg pllx_base;
47 union pllx_misc_reg pllx_misc;
48 union scratch3_reg scratch3;
51 /* enable JTAG & TBE */
52 writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl);
54 /* Are we running where we're supposed to be? */
56 "adr %0, wb_start;" /* reg: wb_start address */
57 : "=r"(reg) /* output */
58 /* no input, no clobber list */
61 if (reg != AP20_WB_RUN_ADDRESS)
64 /* Are we running with AVP? */
65 if (readl(NV_PA_PG_UP_BASE + PG_UP_TAG_0) != PG_UP_TAG_AVP)
68 #ifdef DEBUG_RESET_CORESIGHT
69 /* Assert CoreSight reset */
70 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);
72 writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);
75 /* TODO: Set the drive strength - maybe make this a board parameter? */
76 osc_ctrl.word = readl(&clkrst->crc_osc_ctrl);
79 writel(osc_ctrl.word, &clkrst->crc_osc_ctrl);
81 /* Power up the CPU complex if necessary */
82 if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) {
83 reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START;
84 writel(reg, &pmc->pmc_pwrgate_toggle);
85 while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU))
89 /* Remove the I/O clamps from the CPU power partition. */
90 reg = readl(&pmc->pmc_remove_clamping);
92 writel(reg, &pmc->pmc_remove_clamping);
94 reg = EVENT_ZERO_VAL_20 | EVENT_MSEC | EVENT_MODE_STOP;
95 writel(reg, &flow->halt_cop_events);
97 /* Assert CPU complex reset */
98 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);
100 writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
102 /* Hold both CPUs in reset */
103 reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_CPURESET1 | CPU_CMPLX_DERESET0 |
104 CPU_CMPLX_DERESET1 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DBGRESET1;
105 writel(reg, &clkrst->crc_cpu_cmplx_set);
107 /* Halt CPU1 at the flow controller for uni-processor configurations */
108 writel(EVENT_MODE_STOP, &flow->halt_cpu1_events);
111 * Set the CPU reset vector. SCRATCH41 contains the physical
112 * address of the CPU-side restoration code.
114 reg = readl(&pmc->pmc_scratch41);
115 writel(reg, EXCEP_VECTOR_CPU_RESET_VECTOR);
117 /* Select CPU complex clock source */
118 writel(CCLK_PLLP_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
120 /* Start the CPU0 clock and stop the CPU1 clock */
121 reg = CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 | CPU_CMPLX_CPU0_CLK_STP_RUN |
122 CPU_CMPLX_CPU1_CLK_STP_STOP;
123 writel(reg, &clkrst->crc_clk_cpu_cmplx);
125 /* Enable the CPU complex clock */
126 reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]);
128 writel(reg, &clkrst->crc_clk_out_enb[TEGRA_DEV_L]);
130 /* Make sure the resets were held for at least 2 microseconds */
131 reg = readl(TIMER_USEC_CNTR);
132 while (readl(TIMER_USEC_CNTR) <= (reg + 2))
135 #ifdef DEBUG_RESET_CORESIGHT
137 * De-assert CoreSight reset.
138 * NOTE: We're leaving the CoreSight clock on the oscillator for
139 * now. It will be restored to its original clock source
140 * when the CPU-side restoration code runs.
142 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);
143 reg &= ~SWR_CSITE_RST;
144 writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);
147 /* Unlock the CPU CoreSight interfaces */
149 writel(reg, CSITE_CPU_DBG0_LAR);
150 writel(reg, CSITE_CPU_DBG1_LAR);
153 * Sample the microsecond timestamp again. This is the time we must
154 * use when returning from LP0 for PLL stabilization delays.
156 reg = readl(TIMER_USEC_CNTR);
157 writel(reg, &pmc->pmc_scratch1);
161 scratch3.word = readl(&pmc->pmc_scratch3);
163 /* Get the OSC. For 19.2 MHz, use 19 to make the calculations easier */
164 reg = (readl(TIMER_USEC_CFG) & USEC_CFG_DIVISOR_MASK) + 1;
167 * According to the TRM, for 19.2MHz OSC, the USEC_DIVISOR is 0x5f, and
168 * USEC_DIVIDEND is 0x04. So, if USEC_DIVISOR > 26, OSC is 19.2 MHz.
170 * reg is used to calculate the pllx freq, which is used to determine if
171 * to set dccon or not.
176 /* PLLX_BASE.PLLX_DIVM */
177 if (scratch3.pllx_base_divm == reg)
182 /* PLLX_BASE.PLLX_DIVN */
183 pllx_base.divn = scratch3.pllx_base_divn;
184 reg = scratch3.pllx_base_divn << reg;
186 /* PLLX_BASE.PLLX_DIVP */
187 pllx_base.divp = scratch3.pllx_base_divp;
188 reg = reg >> scratch3.pllx_base_divp;
190 pllx_base.bypass = 1;
192 /* PLLX_MISC_DCCON must be set for pllx frequency > 600 MHz. */
196 /* PLLX_MISC_LFCON */
197 pllx_misc.lfcon = scratch3.pllx_misc_lfcon;
199 /* PLLX_MISC_CPCON */
200 pllx_misc.cpcon = scratch3.pllx_misc_cpcon;
202 writel(pllx_misc.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_misc);
203 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
205 pllx_base.enable = 1;
206 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
207 pllx_base.bypass = 0;
208 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
210 writel(0, flow->halt_cpu_events);
212 reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DERESET0;
213 writel(reg, &clkrst->crc_cpu_cmplx_clr);
215 reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |
216 PLLM_OUT1_RATIO_VAL_8;
217 writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out);
219 reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
220 SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |
222 writel(reg, &clkrst->crc_sclk_brst_pol);
224 /* avp_resume: no return after the write */
225 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);
227 writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
231 reg = EVENT_MODE_STOP | EVENT_JTAG;
232 writel(reg, flow->halt_cop_events);
237 * Execution comes here if something goes wrong. The chip is reset and
238 * a cold boot is performed.
240 writel(SWR_TRIG_SYS_RST, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
245 * wb_end() is a dummy function, and must be directly following wb_start(),
246 * and is used to calculate the size of wb_start().