2 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra30 Clock control functions */
21 #include <asm/arch/clock.h>
22 #include <asm/arch/tegra.h>
23 #include <asm/arch-tegra/clk_rst.h>
24 #include <asm/arch-tegra/timer.h>
29 * Clock types that we can use as a source. The Tegra30 has muxes for the
30 * peripheral clocks, and in most cases there are four options for the clock
31 * source. This gives us a clock 'type' and exploits what commonality exists
34 * Letters are obvious, except for T which means CLK_M, and S which means the
35 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
36 * datasheet) and PLL_M are different things. The former is the basic
37 * clock supplied to the SOC from an external oscillator. The latter is the
40 * See definitions in clock_id in the header file.
43 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
44 CLOCK_TYPE_MCPA, /* and so on */
56 CLOCK_TYPE_NONE = -1, /* invalid clock type */
60 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
64 * Clock source mux for each clock type. This just converts our enum into
65 * a list of mux sources for use by the code.
68 * The extra column in each clock source array is used to store the mask
69 * bits in its register for the source.
71 #define CLK(x) CLOCK_ID_ ## x
72 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
73 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
74 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
76 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
79 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
82 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
85 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
88 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
89 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
91 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
92 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
94 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
95 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
97 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
98 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
100 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
101 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
103 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
104 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
109 * Clock type for each peripheral clock source. We put the name in each
110 * record just so it is easy to match things up
112 #define TYPE(name, type) type
113 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
115 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
116 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
117 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
118 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
119 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
120 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
121 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
122 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
125 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
126 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
127 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
128 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
129 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
130 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
131 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
132 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
135 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
136 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
137 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
138 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
139 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
140 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
141 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
142 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
145 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
146 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
147 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
148 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
149 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
150 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
151 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
152 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
155 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
156 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
157 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
158 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
159 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
160 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
161 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
162 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
165 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
166 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
167 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
168 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
169 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
170 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
171 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
172 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
175 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
176 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
177 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
178 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
179 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
180 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
181 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
182 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
184 /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
185 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
186 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
187 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
188 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
189 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
190 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
191 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
192 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
195 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
196 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
197 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
198 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
199 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
200 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
201 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
202 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
205 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
206 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
207 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
208 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
209 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
210 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
211 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
212 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
215 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
216 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
217 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
218 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
219 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
220 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
221 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
225 * This array translates a periph_id to a periphc_internal_id
227 * Not present/matched up:
228 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
229 * SPDIF - which is both 0x08 and 0x0c
232 #define NONE(name) (-1)
233 #define OFFSET(name, value) PERIPHC_ ## name
234 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
243 PERIPHC_UART2, /* and vfir 0x68 */
248 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
275 /* Middle word: 63:32 */
297 PERIPHC_TVO, /* also CVE 0x40 */
315 /* Upper word 95:64 */
398 NONE(RESERVED0_PCIERX0),
399 NONE(RESERVED1_PCIERX1),
400 NONE(RESERVED2_PCIERX2),
401 NONE(RESERVED3_PCIERX3),
402 NONE(RESERVED4_PCIERX4),
403 NONE(RESERVED5_PCIERX5),
407 NONE(RESERVED6_PCIE2),
409 NONE(RESERVED8_HDMI),
410 NONE(RESERVED9_SATA),
411 NONE(RESERVED10_MIPI),
417 * Get the oscillator frequency, from the corresponding hardware configuration
418 * field. Note that T30 supports 3 new higher freqs, but we map back
419 * to the old T20 freqs. Support for the higher oscillators is TBD.
421 enum clock_osc_freq clock_get_osc_freq(void)
423 struct clk_rst_ctlr *clkrst =
424 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
427 reg = readl(&clkrst->crc_osc_ctrl);
428 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
430 if (reg & 1) /* one of the newer freqs */
431 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
433 return reg >> 2; /* Map to most common (T20) freqs */
436 /* Returns a pointer to the clock source register for a peripheral */
437 u32 *get_periph_source_reg(enum periph_id periph_id)
439 struct clk_rst_ctlr *clkrst =
440 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
441 enum periphc_internal_id internal_id;
443 /* Coresight is a special case */
444 if (periph_id == PERIPH_ID_CSI)
445 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
447 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
448 internal_id = periph_id_to_internal_id[periph_id];
449 assert(internal_id != -1);
450 if (internal_id >= PERIPHC_VW_FIRST) {
451 internal_id -= PERIPHC_VW_FIRST;
452 return &clkrst->crc_clk_src_vw[internal_id];
454 return &clkrst->crc_clk_src[internal_id];
458 * Given a peripheral ID and the required source clock, this returns which
459 * value should be programmed into the source mux for that peripheral.
461 * There is special code here to handle the one source type with 5 sources.
463 * @param periph_id peripheral to start
464 * @param source PLL id of required parent clock
465 * @param mux_bits Set to number of bits in mux register: 2 or 4
466 * @param divider_bits Set to number of divider bits (8 or 16)
467 * @return mux value (0-4, or -1 if not found)
469 int get_periph_clock_source(enum periph_id periph_id,
470 enum clock_id parent, int *mux_bits, int *divider_bits)
472 enum clock_type_id type;
473 enum periphc_internal_id internal_id;
476 assert(clock_periph_id_isvalid(periph_id));
478 internal_id = periph_id_to_internal_id[periph_id];
479 assert(periphc_internal_id_isvalid(internal_id));
481 type = clock_periph_type[internal_id];
482 assert(clock_type_id_isvalid(type));
484 *mux_bits = clock_source[type][CLOCK_MAX_MUX];
486 if (type == CLOCK_TYPE_PCMT16)
491 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
492 if (clock_source[type][mux] == parent)
495 /* if we get here, either us or the caller has made a mistake */
496 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
501 void clock_set_enable(enum periph_id periph_id, int enable)
503 struct clk_rst_ctlr *clkrst =
504 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
508 /* Enable/disable the clock to this peripheral */
509 assert(clock_periph_id_isvalid(periph_id));
510 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
511 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
513 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
516 reg |= PERIPH_MASK(periph_id);
518 reg &= ~PERIPH_MASK(periph_id);
522 void reset_set_enable(enum periph_id periph_id, int enable)
524 struct clk_rst_ctlr *clkrst =
525 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
529 /* Enable/disable reset to the peripheral */
530 assert(clock_periph_id_isvalid(periph_id));
531 if (periph_id < PERIPH_ID_VW_FIRST)
532 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
534 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
537 reg |= PERIPH_MASK(periph_id);
539 reg &= ~PERIPH_MASK(periph_id);
543 #ifdef CONFIG_OF_CONTROL
545 * Convert a device tree clock ID to our peripheral ID. They are mostly
546 * the same but we are very cautious so we check that a valid clock ID is
549 * @param clk_id Clock ID according to tegra30 device tree binding
550 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
552 enum periph_id clk_id_to_periph_id(int clk_id)
554 if (clk_id > PERIPH_ID_COUNT)
555 return PERIPH_ID_NONE;
558 case PERIPH_ID_RESERVED3:
559 case PERIPH_ID_RESERVED4:
560 case PERIPH_ID_RESERVED16:
561 case PERIPH_ID_RESERVED24:
562 case PERIPH_ID_RESERVED35:
563 case PERIPH_ID_RESERVED43:
564 case PERIPH_ID_RESERVED45:
565 case PERIPH_ID_RESERVED56:
566 case PERIPH_ID_RESERVED76:
567 case PERIPH_ID_RESERVED77:
568 case PERIPH_ID_RESERVED78:
569 case PERIPH_ID_RESERVED83:
570 case PERIPH_ID_RESERVED89:
571 case PERIPH_ID_RESERVED91:
572 case PERIPH_ID_RESERVED93:
573 case PERIPH_ID_RESERVED94:
574 case PERIPH_ID_RESERVED95:
575 return PERIPH_ID_NONE;
580 #endif /* CONFIG_OF_CONTROL */
582 void clock_early_init(void)
584 tegra30_set_up_pllp();
587 void arch_timer_init(void)