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1 /*
2  * Copyright (C) 2016 ARM Ltd.
3  * based on the Allwinner H3 dtsi:
4  *      Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5  *
6  * This file is dual-licensed: you can use it either under the terms
7  * of the GPL or the X11 license, at your option. Note that this dual
8  * licensing only applies to this file, and not this project as a
9  * whole.
10  *
11  *  a) This file is free software; you can redistribute it and/or
12  *     modify it under the terms of the GNU General Public License as
13  *     published by the Free Software Foundation; either version 2 of the
14  *     License, or (at your option) any later version.
15  *
16  *     This file is distributed in the hope that it will be useful,
17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  *     GNU General Public License for more details.
20  *
21  * Or, alternatively,
22  *
23  *  b) Permission is hereby granted, free of charge, to any person
24  *     obtaining a copy of this software and associated documentation
25  *     files (the "Software"), to deal in the Software without
26  *     restriction, including without limitation the rights to use,
27  *     copy, modify, merge, publish, distribute, sublicense, and/or
28  *     sell copies of the Software, and to permit persons to whom the
29  *     Software is furnished to do so, subject to the following
30  *     conditions:
31  *
32  *     The above copyright notice and this permission notice shall be
33  *     included in all copies or substantial portions of the Software.
34  *
35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42  *     OTHER DEALINGS IN THE SOFTWARE.
43  */
44
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/pinctrl/sun4i-a10.h>
47
48 / {
49         compatible = "allwinner,a64";
50         interrupt-parent = <&gic>;
51         #address-cells = <1>;
52         #size-cells = <1>;
53
54         aliases {
55                 serial0 = &uart0;
56                 serial1 = &uart1;
57                 serial2 = &uart2;
58                 serial3 = &uart3;
59                 serial4 = &uart4;
60         };
61
62         cpus {
63                 #address-cells = <1>;
64                 #size-cells = <0>;
65
66                 cpu@0 {
67                         compatible = "arm,cortex-a53", "arm,armv8";
68                         device_type = "cpu";
69                         reg = <0>;
70                         enable-method = "psci";
71                 };
72
73                 cpu@1 {
74                         compatible = "arm,cortex-a53", "arm,armv8";
75                         device_type = "cpu";
76                         reg = <1>;
77                         enable-method = "psci";
78                 };
79
80                 cpu@2 {
81                         compatible = "arm,cortex-a53", "arm,armv8";
82                         device_type = "cpu";
83                         reg = <2>;
84                         enable-method = "psci";
85                 };
86
87                 cpu@3 {
88                         compatible = "arm,cortex-a53", "arm,armv8";
89                         device_type = "cpu";
90                         reg = <3>;
91                         enable-method = "psci";
92                 };
93         };
94
95         psci {
96                 compatible = "arm,psci-0.2", "arm,psci";
97                 method = "smc";
98                 cpu_suspend = <0xc4000001>;
99                 cpu_off = <0x84000002>;
100                 cpu_on = <0xc4000003>;
101         };
102
103         memory {
104                 device_type = "memory";
105                 reg = <0x40000000 0>;
106         };
107
108         timer {
109                 compatible = "arm,armv8-timer";
110                 interrupts = <GIC_PPI 13
111                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
112                              <GIC_PPI 14
113                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
114                              <GIC_PPI 11
115                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
116                              <GIC_PPI 10
117                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
118         };
119
120         clocks {
121                 #address-cells = <1>;
122                 #size-cells = <1>;
123                 ranges;
124
125                 osc24M: osc24M_clk {
126                         #clock-cells = <0>;
127                         compatible = "fixed-clock";
128                         clock-frequency = <24000000>;
129                         clock-output-names = "osc24M";
130                 };
131
132                 osc32k: osc32k_clk {
133                         #clock-cells = <0>;
134                         compatible = "fixed-clock";
135                         clock-frequency = <32768>;
136                         clock-output-names = "osc32k";
137                 };
138
139                 pll1: clk@01c20000 {
140                         #clock-cells = <0>;
141                         compatible = "allwinner,sun8i-a23-pll1-clk";
142                         reg = <0x01c20000 0x4>;
143                         clocks = <&osc24M>;
144                         clock-output-names = "pll1";
145                 };
146
147                 pll6: clk@01c20028 {
148                         #clock-cells = <1>;
149                         compatible = "allwinner,sun6i-a31-pll6-clk";
150                         reg = <0x01c20028 0x4>;
151                         clocks = <&osc24M>;
152                         clock-output-names = "pll6", "pll6x2";
153                 };
154
155                 pll6d2: pll6d2_clk {
156                         #clock-cells = <0>;
157                         compatible = "fixed-factor-clock";
158                         clock-div = <2>;
159                         clock-mult = <1>;
160                         clocks = <&pll6 0>;
161                         clock-output-names = "pll6d2";
162                 };
163
164                 /* dummy clock until pll6 can be reused */
165                 pll8: pll8_clk {
166                         #clock-cells = <0>;
167                         compatible = "fixed-clock";
168                         clock-frequency = <1>;
169                         clock-output-names = "pll8";
170                 };
171
172                 cpu: cpu_clk@01c20050 {
173                         #clock-cells = <0>;
174                         compatible = "allwinner,sun4i-a10-cpu-clk";
175                         reg = <0x01c20050 0x4>;
176                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
177                         clock-output-names = "cpu";
178                 };
179
180                 axi: axi_clk@01c20050 {
181                         #clock-cells = <0>;
182                         compatible = "allwinner,sun4i-a10-axi-clk";
183                         reg = <0x01c20050 0x4>;
184                         clocks = <&cpu>;
185                         clock-output-names = "axi";
186                 };
187
188                 ahb1: ahb1_clk@01c20054 {
189                         #clock-cells = <0>;
190                         compatible = "allwinner,sun6i-a31-ahb1-clk";
191                         reg = <0x01c20054 0x4>;
192                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
193                         clock-output-names = "ahb1";
194                 };
195
196                 ahb2: ahb2_clk@01c2005c {
197                         #clock-cells = <0>;
198                         compatible = "allwinner,sun8i-h3-ahb2-clk";
199                         reg = <0x01c2005c 0x4>;
200                         clocks = <&ahb1>, <&pll6d2>;
201                         clock-output-names = "ahb2";
202                 };
203
204                 apb1: apb1_clk@01c20054 {
205                         #clock-cells = <0>;
206                         compatible = "allwinner,sun4i-a10-apb0-clk";
207                         reg = <0x01c20054 0x4>;
208                         clocks = <&ahb1>;
209                         clock-output-names = "apb1";
210                 };
211
212                 apb2: apb2_clk@01c20058 {
213                         #clock-cells = <0>;
214                         compatible = "allwinner,sun4i-a10-apb1-clk";
215                         reg = <0x01c20058 0x4>;
216                         clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
217                         clock-output-names = "apb2";
218                 };
219
220                 bus_gates: clk@01c20060 {
221                         #clock-cells = <1>;
222                         compatible = "allwinner,a64-bus-gates-clk",
223                                      "allwinner,sun8i-h3-bus-gates-clk";
224                         reg = <0x01c20060 0x14>;
225                         clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
226                         clock-names = "ahb1", "ahb2", "apb1", "apb2";
227                         clock-indices = <1>,
228                                         <5>, <6>, <8>,
229                                         <9>, <10>, <13>,
230                                         <14>, <17>, <18>,
231                                         <19>, <20>,
232                                         <21>, <23>,
233                                         <24>, <25>,
234                                         <28>, <29>,
235                                         <32>, <35>,
236                                         <36>, <37>,
237                                         <40>, <43>,
238                                         <44>, <52>, <53>,
239                                         <54>, <64>,
240                                         <65>, <69>, <72>,
241                                         <76>, <77>, <78>,
242                                         <96>, <97>, <98>,
243                                         <101>,
244                                         <112>, <113>,
245                                         <114>, <115>,
246                                         <116>, <135>;
247                         clock-output-names = "bus_mipidsi",
248                                              "bus_ce", "bus_dma", "bus_mmc0",
249                                              "bus_mmc1", "bus_mmc2", "bus_nand",
250                                              "bus_sdram", "bus_gmac", "bus_ts",
251                                              "bus_hstimer", "bus_spi0",
252                                              "bus_spi1", "bus_otg",
253                                              "bus_otg_ehci0", "bus_ehci0",
254                                              "bus_otg_ohci0", "bus_ohci0",
255                                              "bus_ve", "bus_lcd0",
256                                              "bus_lcd1", "bus_deint",
257                                              "bus_csi", "bus_hdmi",
258                                              "bus_de", "bus_gpu", "bus_msgbox",
259                                              "bus_spinlock", "bus_codec",
260                                              "bus_spdif", "bus_pio", "bus_ths",
261                                              "bus_i2s0", "bus_i2s1", "bus_i2s2",
262                                              "bus_i2c0", "bus_i2c1", "bus_i2c2",
263                                              "bus_scr",
264                                              "bus_uart0", "bus_uart1",
265                                              "bus_uart2", "bus_uart3",
266                                              "bus_uart4", "bus_dbg";
267                 };
268
269                 mmc0_clk: clk@01c20088 {
270                         #clock-cells = <1>;
271                         compatible = "allwinner,sun4i-a10-mmc-clk";
272                         reg = <0x01c20088 0x4>;
273                         clocks = <&osc24M>, <&pll6 0>, <&pll8>;
274                         clock-output-names = "mmc0",
275                                              "mmc0_output",
276                                              "mmc0_sample";
277                 };
278
279                 mmc1_clk: clk@01c2008c {
280                         #clock-cells = <1>;
281                         compatible = "allwinner,sun4i-a10-mmc-clk";
282                         reg = <0x01c2008c 0x4>;
283                         clocks = <&osc24M>, <&pll6 0>, <&pll8>;
284                         clock-output-names = "mmc1",
285                                              "mmc1_output",
286                                              "mmc1_sample";
287                 };
288
289                 mmc2_clk: clk@01c20090 {
290                         #clock-cells = <1>;
291                         compatible = "allwinner,sun4i-a10-mmc-clk";
292                         reg = <0x01c20090 0x4>;
293                         clocks = <&osc24M>, <&pll6 0>, <&pll8>;
294                         clock-output-names = "mmc2",
295                                              "mmc2_output",
296                                              "mmc2_sample";
297                 };
298         };
299
300         regulators {
301                 reg_vcc3v3: vcc3v3 {
302                         compatible = "regulator-fixed";
303                         regulator-name = "vcc3v3";
304                         regulator-min-microvolt = <3300000>;
305                         regulator-max-microvolt = <3300000>;
306                 };
307         };
308
309         soc {
310                 compatible = "simple-bus";
311                 #address-cells = <1>;
312                 #size-cells = <1>;
313                 ranges;
314
315                 mmc0: mmc@01c0f000 {
316                         compatible = "allwinner,sun5i-a13-mmc";
317                         reg = <0x01c0f000 0x1000>;
318                         clocks = <&bus_gates 8>,
319                                  <&mmc0_clk 0>,
320                                  <&mmc0_clk 1>,
321                                  <&mmc0_clk 2>;
322                         clock-names = "ahb",
323                                       "mmc",
324                                       "output",
325                                       "sample";
326                         resets = <&ahb_rst 8>;
327                         reset-names = "ahb";
328                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
329                         status = "disabled";
330                         #address-cells = <1>;
331                         #size-cells = <0>;
332                 };
333
334                 mmc1: mmc@01c10000 {
335                         compatible = "allwinner,sun5i-a13-mmc";
336                         reg = <0x01c10000 0x1000>;
337                         clocks = <&bus_gates 9>,
338                                  <&mmc1_clk 0>,
339                                  <&mmc1_clk 1>,
340                                  <&mmc1_clk 2>;
341                         clock-names = "ahb",
342                                       "mmc",
343                                       "output",
344                                       "sample";
345                         resets = <&ahb_rst 9>;
346                         reset-names = "ahb";
347                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
348                         status = "disabled";
349                         #address-cells = <1>;
350                         #size-cells = <0>;
351                 };
352
353                 mmc2: mmc@01c11000 {
354                         compatible = "allwinner,sun5i-a13-mmc";
355                         reg = <0x01c11000 0x1000>;
356                         clocks = <&bus_gates 10>,
357                                  <&mmc2_clk 0>,
358                                  <&mmc2_clk 1>,
359                                  <&mmc2_clk 2>;
360                         clock-names = "ahb",
361                                       "mmc",
362                                       "output",
363                                       "sample";
364                         resets = <&ahb_rst 10>;
365                         reset-names = "ahb";
366                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
367                         status = "disabled";
368                         #address-cells = <1>;
369                         #size-cells = <0>;
370                 };
371
372                 pio: pinctrl@01c20800 {
373                         compatible = "allwinner,a64-pinctrl";
374                         reg = <0x01c20800 0x400>;
375                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
376                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
377                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
378                         clocks = <&bus_gates 69>;
379                         gpio-controller;
380                         #gpio-cells = <3>;
381                         interrupt-controller;
382                         #interrupt-cells = <2>;
383
384                         uart0_pins_a: uart0@0 {
385                                 allwinner,pins = "PB8", "PB9";
386                                 allwinner,function = "uart0";
387                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
388                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
389                         };
390
391                         uart0_pins_b: uart0@1 {
392                                 allwinner,pins = "PF2", "PF3";
393                                 allwinner,function = "uart0";
394                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
395                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
396                         };
397
398                         uart1_pins: uart1@0 {
399                                 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
400                                 allwinner,function = "uart1";
401                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
402                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
403                         };
404
405                         uart2_pins: uart2@0 {
406                                 allwinner,pins = "PB0", "PB1", "PB2", "PB3";
407                                 allwinner,function = "uart2";
408                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
409                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
410                         };
411
412                         uart3_pins_a: uart3@0 {
413                                 allwinner,pins = "PD0", "PD1";
414                                 allwinner,function = "uart3";
415                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
416                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
417                         };
418
419                         uart3_pins_b: uart3@1 {
420                                 allwinner,pins = "PH4", "PH5", "PH6", "PH7";
421                                 allwinner,function = "uart3";
422                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
423                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
424                         };
425
426                         uart4_pins: uart4@0 {
427                                 allwinner,pins = "PD2", "PD3", "PD4", "PD5";
428                                 allwinner,function = "uart4";
429                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
430                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
431                         };
432
433                         mmc0_pins: mmc0@0 {
434                                 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
435                                                  "PF4", "PF5";
436                                 allwinner,function = "mmc0";
437                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
438                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
439                         };
440
441                         mmc0_default_cd_pin: mmc0_cd_pin@0 {
442                                 allwinner,pins = "PF6";
443                                 allwinner,function = "gpio_in";
444                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
445                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
446                         };
447
448                         mmc1_pins: mmc1@0 {
449                                 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
450                                                  "PG4", "PG5";
451                                 allwinner,function = "mmc1";
452                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
453                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
454                         };
455
456                         mmc2_pins: mmc2@0 {
457                                 allwinner,pins = "PC1", "PC5", "PC6", "PC8",
458                                                  "PC9", "PC10";
459                                 allwinner,function = "mmc2";
460                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
461                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
462                         };
463                 };
464
465                 ahb_rst: reset@01c202c0 {
466                         #reset-cells = <1>;
467                         compatible = "allwinner,sun6i-a31-ahb1-reset";
468                         reg = <0x01c202c0 0xc>;
469                 };
470
471                 apb1_rst: reset@01c202d0 {
472                         #reset-cells = <1>;
473                         compatible = "allwinner,sun6i-a31-clock-reset";
474                         reg = <0x01c202d0 0x4>;
475                 };
476
477                 apb2_rst: reset@01c202d8 {
478                         #reset-cells = <1>;
479                         compatible = "allwinner,sun6i-a31-clock-reset";
480                         reg = <0x01c202d8 0x4>;
481                 };
482
483                 uart0: serial@01c28000 {
484                         compatible = "snps,dw-apb-uart";
485                         reg = <0x01c28000 0x400>;
486                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
487                         reg-shift = <2>;
488                         reg-io-width = <4>;
489                         clocks = <&bus_gates 112>;
490                         resets = <&apb2_rst 16>;
491                         reset-names = "apb2";
492                         status = "disabled";
493                 };
494
495                 uart1: serial@01c28400 {
496                         compatible = "snps,dw-apb-uart";
497                         reg = <0x01c28400 0x400>;
498                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
499                         reg-shift = <2>;
500                         reg-io-width = <4>;
501                         clocks = <&bus_gates 113>;
502                         resets = <&apb2_rst 17>;
503                         reset-names = "apb2";
504                         status = "disabled";
505                 };
506
507                 uart2: serial@01c28800 {
508                         compatible = "snps,dw-apb-uart";
509                         reg = <0x01c28800 0x400>;
510                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
511                         reg-shift = <2>;
512                         reg-io-width = <4>;
513                         clocks = <&bus_gates 114>;
514                         resets = <&apb2_rst 18>;
515                         reset-names = "apb2";
516                         status = "disabled";
517                 };
518
519                 uart3: serial@01c28c00 {
520                         compatible = "snps,dw-apb-uart";
521                         reg = <0x01c28c00 0x400>;
522                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
523                         reg-shift = <2>;
524                         reg-io-width = <4>;
525                         clocks = <&bus_gates 115>;
526                         resets = <&apb2_rst 19>;
527                         reset-names = "apb2";
528                         status = "disabled";
529                 };
530
531                 uart4: serial@01c29000 {
532                         compatible = "snps,dw-apb-uart";
533                         reg = <0x01c29000 0x400>;
534                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
535                         reg-shift = <2>;
536                         reg-io-width = <4>;
537                         clocks = <&bus_gates 116>;
538                         resets = <&apb2_rst 20>;
539                         reset-names = "apb2";
540                         status = "disabled";
541                 };
542
543                 rtc: rtc@01f00000 {
544                         compatible = "allwinner,sun6i-a31-rtc";
545                         reg = <0x01f00000 0x54>;
546                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
547                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
548                 };
549         };
550
551         gic: interrupt-controller@{
552                 compatible = "arm,gic-400";
553                 interrupt-controller;
554                 #interrupt-cells = <3>;
555                 #address-cells = <0>;
556
557                 reg = <0x01C81000 0x1000>,
558                       <0x01C82000 0x2000>,
559                       <0x01C84000 0x2000>,
560                       <0x01C86000 0x2000>;
561                 interrupts = <GIC_PPI 9
562                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
563         };
564 };