git.sur5r.net Git - u-boot/blob - arch/arm/dts/am335x-evm.dts

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "am33xx.dtsi"
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12
  13 / {
  14         model = "TI AM335x EVM";
  15         compatible = "ti,am335x-evm", "ti,am33xx";
  16
  17         chosen {
  18                 stdout-path = &uart0;
  19                 tick-timer = &timer2;
  20         };
  21
  22         cpus {
  23                 cpu@0 {
  24                         cpu0-supply = <&vdd1_reg>;
  25                 };
  26         };
  27
  28         memory {
  29                 device_type = "memory";
  30                 reg = <0x80000000 0x10000000>; /* 256 MB */
  31         };
  32
  33         vbat: fixedregulator@0 {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "vbat";
  36                 regulator-min-microvolt = <5000000>;
  37                 regulator-max-microvolt = <5000000>;
  38                 regulator-boot-on;
  39         };
  40
  41         lis3_reg: fixedregulator@1 {
  42                 compatible = "regulator-fixed";
  43                 regulator-name = "lis3_reg";
  44                 regulator-boot-on;
  45         };
  46
  47         wlan_en_reg: fixedregulator@2 {
  48                 compatible = "regulator-fixed";
  49                 regulator-name = "wlan-en-regulator";
  50                 regulator-min-microvolt = <1800000>;
  51                 regulator-max-microvolt = <1800000>;
  52
  53                 /* WLAN_EN GPIO for this board - Bank1, pin16 */
  54                 gpio = <&gpio1 16 0>;
  55
  56                 /* WLAN card specific delay */
  57                 startup-delay-us = <70000>;
  58                 enable-active-high;
  59         };
  60
  61         matrix_keypad: matrix_keypad@0 {
  62                 compatible = "gpio-matrix-keypad";
  63                 debounce-delay-ms = <5>;
  64                 col-scan-delay-us = <2>;
  65
  66                 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH         /* Bank1, pin25 */
  67                              &gpio1 26 GPIO_ACTIVE_HIGH         /* Bank1, pin26 */
  68                              &gpio1 27 GPIO_ACTIVE_HIGH>;       /* Bank1, pin27 */
  69
  70                 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH         /* Bank1, pin21 */
  71                              &gpio1 22 GPIO_ACTIVE_HIGH>;       /* Bank1, pin22 */
  72
  73                 linux,keymap = <0x0000008b      /* MENU */
  74                                 0x0100009e      /* BACK */
  75                                 0x02000069      /* LEFT */
  76                                 0x0001006a      /* RIGHT */
  77                                 0x0101001c      /* ENTER */
  78                                 0x0201006c>;    /* DOWN */
  79         };
  80
  81         gpio_keys: volume_keys@0 {
  82                 compatible = "gpio-keys";
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85                 autorepeat;
  86
  87                 switch@9 {
  88                         label = "volume-up";
  89                         linux,code = <115>;
  90                         gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  91                         gpio-key,wakeup;
  92                 };
  93
  94                 switch@10 {
  95                         label = "volume-down";
  96                         linux,code = <114>;
  97                         gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
  98                         gpio-key,wakeup;
  99                 };
 100         };
 101
 102         backlight {
 103                 compatible = "pwm-backlight";
 104                 pwms = <&ecap0 0 50000 0>;
 105                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
 106                 default-brightness-level = <8>;
 107         };
 108
 109         panel {
 110                 compatible = "ti,tilcdc,panel";
 111                 status = "okay";
 112                 pinctrl-names = "default";
 113                 pinctrl-0 = <&lcd_pins_s0>;
 114                 panel-info {
 115                         ac-bias           = <255>;
 116                         ac-bias-intrpt    = <0>;
 117                         dma-burst-sz      = <16>;
 118                         bpp               = <32>;
 119                         fdd               = <0x80>;
 120                         sync-edge         = <0>;
 121                         sync-ctrl         = <1>;
 122                         raster-order      = <0>;
 123                         fifo-th           = <0>;
 124                 };
 125
 126                 display-timings {
 127                         800x480p62 {
 128                                 clock-frequency = <30000000>;
 129                                 hactive = <800>;
 130                                 vactive = <480>;
 131                                 hfront-porch = <39>;
 132                                 hback-porch = <39>;
 133                                 hsync-len = <47>;
 134                                 vback-porch = <29>;
 135                                 vfront-porch = <13>;
 136                                 vsync-len = <2>;
 137                                 hsync-active = <1>;
 138                                 vsync-active = <1>;
 139                         };
 140                 };
 141         };
 142
 143         sound {
 144                 compatible = "ti,da830-evm-audio";
 145                 ti,model = "AM335x-EVM";
 146                 ti,audio-codec = <&tlv320aic3106>;
 147                 ti,mcasp-controller = <&mcasp1>;
 148                 ti,codec-clock-rate = <12000000>;
 149                 ti,audio-routing =
 150                         "Headphone Jack",       "HPLOUT",
 151                         "Headphone Jack",       "HPROUT",
 152                         "LINE1L",               "Line In",
 153                         "LINE1R",               "Line In";
 154         };
 155 };
 156
 157 &am33xx_pinmux {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
 160
 161         matrix_keypad_s0: matrix_keypad_s0 {
 162                 pinctrl-single,pins = <
 163                         0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
 164                         0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a6.gpio1_22 */
 165                         0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a9.gpio1_25 */
 166                         0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a10.gpio1_26 */
 167                         0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a11.gpio1_27 */
 168                 >;
 169         };
 170
 171         volume_keys_s0: volume_keys_s0 {
 172                 pinctrl-single,pins = <
 173                         0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_sclk.gpio0_2 */
 174                         0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_d0.gpio0_3 */
 175                 >;
 176         };
 177
 178         i2c0_pins: pinmux_i2c0_pins {
 179                 pinctrl-single,pins = <
 180                         0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
 181                         0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
 182                 >;
 183         };
 184
 185         i2c1_pins: pinmux_i2c1_pins {
 186                 pinctrl-single,pins = <
 187                         0x158 (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_d1.i2c1_sda */
 188                         0x15c (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_cs0.i2c1_scl */
 189                 >;
 190         };
 191
 192         uart0_pins: pinmux_uart0_pins {
 193                 pinctrl-single,pins = <
 194                         0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
 195                         0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
 196                 >;
 197         };
 198
 199         uart1_pins: pinmux_uart1_pins {
 200                 pinctrl-single,pins = <
 201                         0x178 (PIN_INPUT | MUX_MODE0)           /* uart1_ctsn.uart1_ctsn */
 202                         0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
 203                         0x180 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart1_rxd.uart1_rxd */
 204                         0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
 205                 >;
 206         };
 207
 208         clkout2_pin: pinmux_clkout2_pin {
 209                 pinctrl-single,pins = <
 210                         0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
 211                 >;
 212         };
 213
 214         nandflash_pins_s0: nandflash_pins_s0 {
 215                 pinctrl-single,pins = <
 216                         0x0 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad0.gpmc_ad0 */
 217                         0x4 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad1.gpmc_ad1 */
 218                         0x8 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad2.gpmc_ad2 */
 219                         0xc (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad3.gpmc_ad3 */
 220                         0x10 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
 221                         0x14 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
 222                         0x18 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
 223                         0x1c (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
 224                         0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
 225                         0x74 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_wpn.gpio0_30 */
 226                         0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
 227                         0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
 228                         0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
 229                         0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
 230                         0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
 231                 >;
 232         };
 233
 234         ecap0_pins: backlight_pins {
 235                 pinctrl-single,pins = <
 236                         0x164 0x0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 237                 >;
 238         };
 239
 240         cpsw_default: cpsw_default {
 241                 pinctrl-single,pins = <
 242                         /* Slave 1 */
 243                         0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
 244                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
 245                         0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
 246                         0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
 247                         0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
 248                         0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
 249                         0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
 250                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
 251                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
 252                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
 253                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
 254                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
 255                 >;
 256         };
 257
 258         cpsw_sleep: cpsw_sleep {
 259                 pinctrl-single,pins = <
 260                         /* Slave 1 reset value */
 261                         0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 262                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 263                         0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 264                         0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 265                         0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 266                         0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 267                         0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 268                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 269                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 270                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 271                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 272                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 273                 >;
 274         };
 275
 276         davinci_mdio_default: davinci_mdio_default {
 277                 pinctrl-single,pins = <
 278                         /* MDIO */
 279                         0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
 280                         0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
 281                 >;
 282         };
 283
 284         davinci_mdio_sleep: davinci_mdio_sleep {
 285                 pinctrl-single,pins = <
 286                         /* MDIO reset value */
 287                         0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 288                         0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 289                 >;
 290         };
 291
 292         mmc1_pins: pinmux_mmc1_pins {
 293                 pinctrl-single,pins = <
 294                         0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 295                 >;
 296         };
 297
 298         mmc3_pins: pinmux_mmc3_pins {
 299                 pinctrl-single,pins = <
 300                         0x44 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
 301                         0x48 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
 302                         0x4C (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
 303                         0x78 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
 304                         0x88 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
 305                         0x8C (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
 306                 >;
 307         };
 308
 309         wlan_pins: pinmux_wlan_pins {
 310                 pinctrl-single,pins = <
 311                         0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a0.gpio1_16 */
 312                         0x19C (PIN_INPUT | MUX_MODE7)           /* mcasp0_ahclkr.gpio3_17 */
 313                         0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
 314                 >;
 315         };
 316
 317         lcd_pins_s0: lcd_pins_s0 {
 318                 pinctrl-single,pins = <
 319                         0x20 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad8.lcd_data23 */
 320                         0x24 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad9.lcd_data22 */
 321                         0x28 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad10.lcd_data21 */
 322                         0x2c (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad11.lcd_data20 */
 323                         0x30 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad12.lcd_data19 */
 324                         0x34 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad13.lcd_data18 */
 325                         0x38 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad14.lcd_data17 */
 326                         0x3c (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad15.lcd_data16 */
 327                         0xa0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data0.lcd_data0 */
 328                         0xa4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data1.lcd_data1 */
 329                         0xa8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data2.lcd_data2 */
 330                         0xac (PIN_OUTPUT | MUX_MODE0)           /* lcd_data3.lcd_data3 */
 331                         0xb0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data4.lcd_data4 */
 332                         0xb4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data5.lcd_data5 */
 333                         0xb8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data6.lcd_data6 */
 334                         0xbc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data7.lcd_data7 */
 335                         0xc0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data8.lcd_data8 */
 336                         0xc4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data9.lcd_data9 */
 337                         0xc8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data10.lcd_data10 */
 338                         0xcc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data11.lcd_data11 */
 339                         0xd0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data12.lcd_data12 */
 340                         0xd4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data13.lcd_data13 */
 341                         0xd8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data14.lcd_data14 */
 342                         0xdc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data15.lcd_data15 */
 343                         0xe0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_vsync.lcd_vsync */
 344                         0xe4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_hsync.lcd_hsync */
 345                         0xe8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_pclk.lcd_pclk */
 346                         0xec (PIN_OUTPUT | MUX_MODE0)           /* lcd_ac_bias_en.lcd_ac_bias_en */
 347                 >;
 348         };
 349
 350         am335x_evm_audio_pins: am335x_evm_audio_pins {
 351                 pinctrl-single,pins = <
 352                         0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
 353                         0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
 354                         0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
 355                         0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
 356                 >;
 357         };
 358
 359         dcan1_pins_default: dcan1_pins_default {
 360                 pinctrl-single,pins = <
 361                         0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
 362                         0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
 363                 >;
 364         };
 365 };
 366
 367 &uart0 {
 368         pinctrl-names = "default";
 369         pinctrl-0 = <&uart0_pins>;
 370
 371         status = "okay";
 372 };
 373
 374 &uart1 {
 375         pinctrl-names = "default";
 376         pinctrl-0 = <&uart1_pins>;
 377
 378         status = "okay";
 379 };
 380
 381 &i2c0 {
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&i2c0_pins>;
 384
 385         status = "okay";
 386         clock-frequency = <400000>;
 387
 388         tps: tps@2d {
 389                 reg = <0x2d>;
 390         };
 391 };
 392
 393 &usb {
 394         status = "okay";
 395 };
 396
 397 &usb_ctrl_mod {
 398         status = "okay";
 399 };
 400
 401 &usb0_phy {
 402         status = "okay";
 403 };
 404
 405 &usb1_phy {
 406         status = "okay";
 407 };
 408
 409 &usb0 {
 410         status = "okay";
 411 };
 412
 413 &usb1 {
 414         status = "okay";
 415         dr_mode = "host";
 416 };
 417
 418 &cppi41dma  {
 419         status = "okay";
 420 };
 421
 422 &i2c1 {
 423         pinctrl-names = "default";
 424         pinctrl-0 = <&i2c1_pins>;
 425
 426         status = "okay";
 427         clock-frequency = <100000>;
 428
 429         lis331dlh: lis331dlh@18 {
 430                 compatible = "st,lis331dlh", "st,lis3lv02d";
 431                 reg = <0x18>;
 432                 Vdd-supply = <&lis3_reg>;
 433                 Vdd_IO-supply = <&lis3_reg>;
 434
 435                 st,click-single-x;
 436                 st,click-single-y;
 437                 st,click-single-z;
 438                 st,click-thresh-x = <10>;
 439                 st,click-thresh-y = <10>;
 440                 st,click-thresh-z = <10>;
 441                 st,irq1-click;
 442                 st,irq2-click;
 443                 st,wakeup-x-lo;
 444                 st,wakeup-x-hi;
 445                 st,wakeup-y-lo;
 446                 st,wakeup-y-hi;
 447                 st,wakeup-z-lo;
 448                 st,wakeup-z-hi;
 449                 st,min-limit-x = <120>;
 450                 st,min-limit-y = <120>;
 451                 st,min-limit-z = <140>;
 452                 st,max-limit-x = <550>;
 453                 st,max-limit-y = <550>;
 454                 st,max-limit-z = <750>;
 455         };
 456
 457         tsl2550: tsl2550@39 {
 458                 compatible = "taos,tsl2550";
 459                 reg = <0x39>;
 460         };
 461
 462         tmp275: tmp275@48 {
 463                 compatible = "ti,tmp275";
 464                 reg = <0x48>;
 465         };
 466
 467         tlv320aic3106: tlv320aic3106@1b {
 468                 compatible = "ti,tlv320aic3106";
 469                 reg = <0x1b>;
 470                 status = "okay";
 471
 472                 /* Regulators */
 473                 AVDD-supply = <&vaux2_reg>;
 474                 IOVDD-supply = <&vaux2_reg>;
 475                 DRVDD-supply = <&vaux2_reg>;
 476                 DVDD-supply = <&vbat>;
 477         };
 478 };
 479
 480 &lcdc {
 481         status = "okay";
 482 };
 483
 484 &elm {
 485         status = "okay";
 486 };
 487
 488 &epwmss0 {
 489         status = "okay";
 490
 491         ecap0: ecap@48300100 {
 492                 status = "okay";
 493                 pinctrl-names = "default";
 494                 pinctrl-0 = <&ecap0_pins>;
 495         };
 496 };
 497
 498 &gpmc {
 499         status = "okay";
 500         pinctrl-names = "default";
 501         pinctrl-0 = <&nandflash_pins_s0>;
 502         ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
 503         nand@0,0 {
 504                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 505                 ti,nand-ecc-opt = "bch8";
 506                 ti,elm-id = <&elm>;
 507                 nand-bus-width = <8>;
 508                 gpmc,device-width = <1>;
 509                 gpmc,sync-clk-ps = <0>;
 510                 gpmc,cs-on-ns = <0>;
 511                 gpmc,cs-rd-off-ns = <44>;
 512                 gpmc,cs-wr-off-ns = <44>;
 513                 gpmc,adv-on-ns = <6>;
 514                 gpmc,adv-rd-off-ns = <34>;
 515                 gpmc,adv-wr-off-ns = <44>;
 516                 gpmc,we-on-ns = <0>;
 517                 gpmc,we-off-ns = <40>;
 518                 gpmc,oe-on-ns = <0>;
 519                 gpmc,oe-off-ns = <54>;
 520                 gpmc,access-ns = <64>;
 521                 gpmc,rd-cycle-ns = <82>;
 522                 gpmc,wr-cycle-ns = <82>;
 523                 gpmc,wait-on-read = "true";
 524                 gpmc,wait-on-write = "true";
 525                 gpmc,bus-turnaround-ns = <0>;
 526                 gpmc,cycle2cycle-delay-ns = <0>;
 527                 gpmc,clk-activation-ns = <0>;
 528                 gpmc,wait-monitoring-ns = <0>;
 529                 gpmc,wr-access-ns = <40>;
 530                 gpmc,wr-data-mux-bus-ns = <0>;
 531                 /* MTD partition table */
 532                 /* All SPL-* partitions are sized to minimal length
 533                  * which can be independently programmable. For
 534                  * NAND flash this is equal to size of erase-block */
 535                 #address-cells = <1>;
 536                 #size-cells = <1>;
 537                 partition@0 {
 538                         label = "NAND.SPL";
 539                         reg = <0x00000000 0x000020000>;
 540                 };
 541                 partition@1 {
 542                         label = "NAND.SPL.backup1";
 543                         reg = <0x00020000 0x00020000>;
 544                 };
 545                 partition@2 {
 546                         label = "NAND.SPL.backup2";
 547                         reg = <0x00040000 0x00020000>;
 548                 };
 549                 partition@3 {
 550                         label = "NAND.SPL.backup3";
 551                         reg = <0x00060000 0x00020000>;
 552                 };
 553                 partition@4 {
 554                         label = "NAND.u-boot-spl-os";
 555                         reg = <0x00080000 0x00040000>;
 556                 };
 557                 partition@5 {
 558                         label = "NAND.u-boot";
 559                         reg = <0x000C0000 0x00100000>;
 560                 };
 561                 partition@6 {
 562                         label = "NAND.u-boot-env";
 563                         reg = <0x001C0000 0x00020000>;
 564                 };
 565                 partition@7 {
 566                         label = "NAND.u-boot-env.backup1";
 567                         reg = <0x001E0000 0x00020000>;
 568                 };
 569                 partition@8 {
 570                         label = "NAND.kernel";
 571                         reg = <0x00200000 0x00800000>;
 572                 };
 573                 partition@9 {
 574                         label = "NAND.file-system";
 575                         reg = <0x00A00000 0x0F600000>;
 576                 };
 577         };
 578 };
 579
 580 #include "tps65910.dtsi"
 581
 582 &mcasp1 {
 583                 pinctrl-names = "default";
 584                 pinctrl-0 = <&am335x_evm_audio_pins>;
 585
 586                 status = "okay";
 587
 588                 op-mode = <0>;          /* MCASP_IIS_MODE */
 589                 tdm-slots = <2>;
 590                 /* 4 serializers */
 591                 serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 592                         0 0 1 2
 593                 >;
 594                 tx-num-evt = <32>;
 595                 rx-num-evt = <32>;
 596 };
 597
 598 &tps {
 599         vcc1-supply = <&vbat>;
 600         vcc2-supply = <&vbat>;
 601         vcc3-supply = <&vbat>;
 602         vcc4-supply = <&vbat>;
 603         vcc5-supply = <&vbat>;
 604         vcc6-supply = <&vbat>;
 605         vcc7-supply = <&vbat>;
 606         vccio-supply = <&vbat>;
 607
 608         regulators {
 609                 vrtc_reg: regulator@0 {
 610                         regulator-always-on;
 611                 };
 612
 613                 vio_reg: regulator@1 {
 614                         regulator-always-on;
 615                 };
 616
 617                 vdd1_reg: regulator@2 {
 618                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 619                         regulator-name = "vdd_mpu";
 620                         regulator-min-microvolt = <912500>;
 621                         regulator-max-microvolt = <1312500>;
 622                         regulator-boot-on;
 623                         regulator-always-on;
 624                 };
 625
 626                 vdd2_reg: regulator@3 {
 627                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 628                         regulator-name = "vdd_core";
 629                         regulator-min-microvolt = <912500>;
 630                         regulator-max-microvolt = <1150000>;
 631                         regulator-boot-on;
 632                         regulator-always-on;
 633                 };
 634
 635                 vdd3_reg: regulator@4 {
 636                         regulator-always-on;
 637                 };
 638
 639                 vdig1_reg: regulator@5 {
 640                         regulator-always-on;
 641                 };
 642
 643                 vdig2_reg: regulator@6 {
 644                         regulator-always-on;
 645                 };
 646
 647                 vpll_reg: regulator@7 {
 648                         regulator-always-on;
 649                 };
 650
 651                 vdac_reg: regulator@8 {
 652                         regulator-always-on;
 653                 };
 654
 655                 vaux1_reg: regulator@9 {
 656                         regulator-always-on;
 657                 };
 658
 659                 vaux2_reg: regulator@10 {
 660                         regulator-always-on;
 661                 };
 662
 663                 vaux33_reg: regulator@11 {
 664                         regulator-always-on;
 665                 };
 666
 667                 vmmc_reg: regulator@12 {
 668                         regulator-min-microvolt = <1800000>;
 669                         regulator-max-microvolt = <3300000>;
 670                         regulator-always-on;
 671                 };
 672         };
 673 };
 674
 675 &mac {
 676         pinctrl-names = "default", "sleep";
 677         pinctrl-0 = <&cpsw_default>;
 678         pinctrl-1 = <&cpsw_sleep>;
 679         status = "okay";
 680 };
 681
 682 &davinci_mdio {
 683         pinctrl-names = "default", "sleep";
 684         pinctrl-0 = <&davinci_mdio_default>;
 685         pinctrl-1 = <&davinci_mdio_sleep>;
 686         status = "okay";
 687 };
 688
 689 &cpsw_emac0 {
 690         phy_id = <&davinci_mdio>, <0>;
 691         phy-mode = "rgmii-txid";
 692 };
 693
 694 &cpsw_emac1 {
 695         phy_id = <&davinci_mdio>, <1>;
 696         phy-mode = "rgmii-txid";
 697 };
 698
 699 &tscadc {
 700         status = "okay";
 701         tsc {
 702                 ti,wires = <4>;
 703                 ti,x-plate-resistance = <200>;
 704                 ti,coordinate-readouts = <5>;
 705                 ti,wire-config = <0x00 0x11 0x22 0x33>;
 706                 ti,charge-delay = <0x400>;
 707         };
 708
 709         adc {
 710                 ti,adc-channels = <4 5 6 7>;
 711         };
 712 };
 713
 714 &mmc1 {
 715         status = "okay";
 716         vmmc-supply = <&vmmc_reg>;
 717         bus-width = <4>;
 718         pinctrl-names = "default";
 719         pinctrl-0 = <&mmc1_pins>;
 720         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 721 };
 722
 723 &mmc3 {
 724         /* these are on the crossbar and are outlined in the
 725            xbar-event-map element */
 726         dmas = <&edma 12
 727                 &edma 13>;
 728         dma-names = "tx", "rx";
 729         status = "okay";
 730         vmmc-supply = <&wlan_en_reg>;
 731         bus-width = <4>;
 732         pinctrl-names = "default";
 733         pinctrl-0 = <&mmc3_pins &wlan_pins>;
 734         ti,non-removable;
 735         ti,needs-special-hs-handling;
 736         cap-power-off-card;
 737         keep-power-in-suspend;
 738
 739         #address-cells = <1>;
 740         #size-cells = <0>;
 741         wlcore: wlcore@0 {
 742                 compatible = "ti,wl1835";
 743                 reg = <2>;
 744                 interrupt-parent = <&gpio3>;
 745                 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
 746         };
 747 };
 748
 749 &edma {
 750         ti,edma-xbar-event-map = /bits/ 16 <1 12
 751                                             2 13>;
 752 };
 753
 754 &sham {
 755         status = "okay";
 756 };
 757
 758 &aes {
 759         status = "okay";
 760 };
 761
 762 &dcan1 {
 763         status = "disabled";    /* Enable only if Profile 1 is selected */
 764         pinctrl-names = "default";
 765         pinctrl-0 = <&dcan1_pins_default>;
 766 };