git.sur5r.net Git - u-boot/blob - arch/arm/dts/am437x-gp-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /* AM437x GP EVM */
  10
  11 /dts-v1/;
  12
  13 #include "am4372.dtsi"
  14 #include <dt-bindings/pinctrl/am43xx.h>
  15 #include <dt-bindings/pwm/pwm.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17
  18 / {
  19         model = "TI AM437x GP EVM";
  20         compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
  21
  22         aliases {
  23                 display0 = &lcd0;
  24                 serial3 = &uart3;
  25         };
  26
  27         chosen {
  28                 stdout-path = &uart0;
  29                 tick-timer = &timer2;
  30         };
  31
  32         vmmcsd_fixed: fixedregulator-sd {
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "vmmcsd_fixed";
  35                 regulator-min-microvolt = <3300000>;
  36                 regulator-max-microvolt = <3300000>;
  37                 enable-active-high;
  38         };
  39
  40         vtt_fixed: fixedregulator-vtt {
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "vtt_fixed";
  43                 regulator-min-microvolt = <1500000>;
  44                 regulator-max-microvolt = <1500000>;
  45                 regulator-always-on;
  46                 regulator-boot-on;
  47                 enable-active-high;
  48                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  49         };
  50
  51         vmmcwl_fixed: fixedregulator-mmcwl {
  52                 compatible = "regulator-fixed";
  53                 regulator-name = "vmmcwl_fixed";
  54                 regulator-min-microvolt = <1800000>;
  55                 regulator-max-microvolt = <1800000>;
  56                 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  57                 enable-active-high;
  58         };
  59
  60         backlight {
  61                 compatible = "pwm-backlight";
  62                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
  63                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
  64                 default-brightness-level = <8>;
  65         };
  66
  67         matrix_keypad: matrix_keypad@0 {
  68                 compatible = "gpio-matrix-keypad";
  69                 debounce-delay-ms = <5>;
  70                 col-scan-delay-us = <2>;
  71
  72                 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
  73                                 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
  74                                 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
  75
  76                 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
  77                                 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
  78
  79                 linux,keymap = <0x00000201      /* P1 */
  80                                 0x00010202      /* P2 */
  81                                 0x01000067      /* UP */
  82                                 0x0101006a      /* RIGHT */
  83                                 0x02000069      /* LEFT */
  84                                 0x0201006c>;      /* DOWN */
  85                 };
  86
  87         lcd0: display {
  88                 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  89                 label = "lcd";
  90
  91                 pinctrl-names = "default";
  92                 pinctrl-0 = <&lcd_pins>;
  93
  94                 /*
  95                  * SelLCDorHDMI, LOW to select HDMI. This is not really the
  96                  * panel's enable GPIO, but we don't have HDMI driver support nor
  97                  * support to switch between two displays, so using this gpio as
  98                  * panel's enable should be safe.
  99                  */
 100                 enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 101
 102                 panel-timing {
 103                         clock-frequency = <33000000>;
 104                         hactive = <800>;
 105                         vactive = <480>;
 106                         hfront-porch = <210>;
 107                         hback-porch = <16>;
 108                         hsync-len = <30>;
 109                         vback-porch = <10>;
 110                         vfront-porch = <22>;
 111                         vsync-len = <13>;
 112                         hsync-active = <0>;
 113                         vsync-active = <0>;
 114                         de-active = <1>;
 115                         pixelclk-active = <1>;
 116                 };
 117
 118                 port {
 119                         lcd_in: endpoint {
 120                                 remote-endpoint = <&dpi_out>;
 121                         };
 122                 };
 123         };
 124
 125         /* fixed 12MHz oscillator */
 126         refclk: oscillator {
 127                 #clock-cells = <0>;
 128                 compatible = "fixed-clock";
 129                 clock-frequency = <12000000>;
 130         };
 131
 132 };
 133
 134 &am43xx_pinmux {
 135         pinctrl-names = "default", "sleep";
 136         pinctrl-0 = <&wlan_pins_default>;
 137         pinctrl-1 = <&wlan_pins_sleep>;
 138
 139         i2c0_pins: i2c0_pins {
 140                 pinctrl-single,pins = <
 141                         0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
 142                         0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
 143                 >;
 144         };
 145
 146         i2c1_pins: i2c1_pins {
 147                 pinctrl-single,pins = <
 148                         0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
 149                         0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
 150                 >;
 151         };
 152
 153         mmc1_pins: pinmux_mmc1_pins {
 154                 pinctrl-single,pins = <
 155                         0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 156                 >;
 157         };
 158
 159         ecap0_pins: backlight_pins {
 160                 pinctrl-single,pins = <
 161                         0x164 MUX_MODE0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 162                 >;
 163         };
 164
 165         pixcir_ts_pins: pixcir_ts_pins {
 166                 pinctrl-single,pins = <
 167                         0x264 (PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
 168                 >;
 169         };
 170
 171         cpsw_default: cpsw_default {
 172                 pinctrl-single,pins = <
 173                         /* Slave 1 */
 174                         0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
 175                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rxctl */
 176                         0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
 177                         0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
 178                         0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
 179                         0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
 180                         0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
 181                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rmii1_rclk */
 182                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd3 */
 183                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd2 */
 184                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd1 */
 185                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd0 */
 186                 >;
 187         };
 188
 189         cpsw_sleep: cpsw_sleep {
 190                 pinctrl-single,pins = <
 191                         /* Slave 1 reset value */
 192                         0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 193                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 194                         0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 195                         0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 196                         0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 197                         0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 198                         0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 199                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 200                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 201                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 202                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 203                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 204                 >;
 205         };
 206
 207         davinci_mdio_default: davinci_mdio_default {
 208                 pinctrl-single,pins = <
 209                         /* MDIO */
 210                         0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
 211                         0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
 212                 >;
 213         };
 214
 215         davinci_mdio_sleep: davinci_mdio_sleep {
 216                 pinctrl-single,pins = <
 217                         /* MDIO reset value */
 218                         0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 219                         0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 220                 >;
 221         };
 222
 223         nand_flash_x8: nand_flash_x8 {
 224                 pinctrl-single,pins = <
 225                         0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* spi2_cs0.gpio/eMMCorNANDsel */
 226                         0x0  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
 227                         0x4  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
 228                         0x8  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
 229                         0xc  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
 230                         0x10 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
 231                         0x14 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
 232                         0x18 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
 233                         0x1c (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
 234                         0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
 235                         0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
 236                         0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
 237                         0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
 238                         0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
 239                         0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
 240                         0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
 241                 >;
 242         };
 243
 244         dss_pins: dss_pins {
 245                 pinctrl-single,pins = <
 246                         0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
 247                         0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 248                         0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 249                         0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
 250                         0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 251                         0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 252                         0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 253                         0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
 254                         0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
 255                         0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 256                         0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 257                         0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
 258                         0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 259                         0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 260                         0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 261                         0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
 262                         0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 263                         0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 264                         0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 265                         0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
 266                         0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 267                         0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 268                         0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 269                         0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
 270                         0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
 271                         0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
 272                         0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
 273                         0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 274
 275                 >;
 276         };
 277
 278         lcd_pins: lcd_pins {
 279                 pinctrl-single,pins = <
 280                         /* GPIO 5_8 to select LCD / HDMI */
 281                         0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
 282                 >;
 283         };
 284
 285         dcan0_default: dcan0_default_pins {
 286                 pinctrl-single,pins = <
 287                         0x178 (PIN_OUTPUT | MUX_MODE2)          /* uart1_ctsn.d_can0_tx */
 288                         0x17c (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_rtsn.d_can0_rx */
 289                 >;
 290         };
 291
 292         dcan1_default: dcan1_default_pins {
 293                 pinctrl-single,pins = <
 294                         0x180 (PIN_OUTPUT | MUX_MODE2)          /* uart1_rxd.d_can1_tx */
 295                         0x184 (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_txd.d_can1_rx */
 296                 >;
 297         };
 298
 299         vpfe0_pins_default: vpfe0_pins_default {
 300                 pinctrl-single,pins = <
 301                         0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
 302                         0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
 303                         0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
 304                         0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
 305                         0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
 306                         0x208 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
 307                         0x20C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
 308                         0x210 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
 309                         0x214 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
 310                         0x218 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
 311                         0x21C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
 312                         0x220 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
 313                         0x224 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
 314                 >;
 315         };
 316
 317         vpfe0_pins_sleep: vpfe0_pins_sleep {
 318                 pinctrl-single,pins = <
 319                         0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
 320                         0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
 321                         0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
 322                         0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
 323                         0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
 324                         0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
 325                         0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
 326                         0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
 327                         0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
 328                         0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
 329                         0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
 330                         0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
 331                         0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
 332                 >;
 333         };
 334
 335         vpfe1_pins_default: vpfe1_pins_default {
 336                 pinctrl-single,pins = <
 337                         0x1CC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
 338                         0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
 339                         0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
 340                         0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
 341                         0x1DC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
 342                         0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
 343                         0x1EC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
 344                         0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
 345                         0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
 346                         0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
 347                         0x1FC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
 348                         0x200 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
 349                         0x204 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
 350                 >;
 351         };
 352
 353         vpfe1_pins_sleep: vpfe1_pins_sleep {
 354                 pinctrl-single,pins = <
 355                         0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
 356                         0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
 357                         0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
 358                         0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
 359                         0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
 360                         0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
 361                         0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
 362                         0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
 363                         0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
 364                         0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
 365                         0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
 366                         0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
 367                         0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
 368                 >;
 369         };
 370
 371         mmc3_pins_default: pinmux_mmc3_pins_default {
 372                 pinctrl-single,pins = <
 373                         0x8c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
 374                         0x88 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
 375                         0x44 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
 376                         0x48 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
 377                         0x4c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
 378                         0x78 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
 379                 >;
 380         };
 381
 382         mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
 383                 pinctrl-single,pins = <
 384                         0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_clk.mmc2_clk */
 385                         0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_csn3.mmc2_cmd */
 386                         0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a1.mmc2_dat0 */
 387                         0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a2.mmc2_dat1 */
 388                         0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a3.mmc2_dat2 */
 389                         0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_be1n.mmc2_dat3 */
 390                 >;
 391         };
 392
 393         wlan_pins_default: pinmux_wlan_pins_default {
 394                 pinctrl-single,pins = <
 395                         0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a4.gpio1_20 WL_EN */
 396                         0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)    /* gpmc_a7.gpio1_23 WL_IRQ*/
 397                         0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a0.gpio1_16 BT_EN*/
 398                 >;
 399         };
 400
 401         wlan_pins_sleep: pinmux_wlan_pins_sleep {
 402                 pinctrl-single,pins = <
 403                         0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a4.gpio1_20 WL_EN */
 404                         0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)    /* gpmc_a7.gpio1_23 WL_IRQ*/
 405                         0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7)            /* gpmc_a0.gpio1_16 BT_EN*/
 406                 >;
 407         };
 408
 409         uart3_pins: uart3_pins {
 410                 pinctrl-single,pins = <
 411                         0x228 (PIN_INPUT | MUX_MODE0)           /* uart3_rxd.uart3_rxd */
 412                         0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
 413                         0x230 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart3_ctsn.uart3_ctsn */
 414                         0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
 415                 >;
 416         };
 417 };
 418
 419 &i2c0 {
 420         status = "okay";
 421         pinctrl-names = "default";
 422         pinctrl-0 = <&i2c0_pins>;
 423         clock-frequency = <100000>;
 424
 425         tps65218: tps65218@24 {
 426                 reg = <0x24>;
 427                 compatible = "ti,tps65218";
 428                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
 429                 interrupt-controller;
 430                 #interrupt-cells = <2>;
 431
 432                 dcdc1: regulator-dcdc1 {
 433                         compatible = "ti,tps65218-dcdc1";
 434                         regulator-name = "vdd_core";
 435                         regulator-min-microvolt = <912000>;
 436                         regulator-max-microvolt = <1144000>;
 437                         regulator-boot-on;
 438                         regulator-always-on;
 439                 };
 440
 441                 dcdc2: regulator-dcdc2 {
 442                         compatible = "ti,tps65218-dcdc2";
 443                         regulator-name = "vdd_mpu";
 444                         regulator-min-microvolt = <912000>;
 445                         regulator-max-microvolt = <1378000>;
 446                         regulator-boot-on;
 447                         regulator-always-on;
 448                 };
 449
 450                 dcdc3: regulator-dcdc3 {
 451                         compatible = "ti,tps65218-dcdc3";
 452                         regulator-name = "vdcdc3";
 453                         regulator-min-microvolt = <1500000>;
 454                         regulator-max-microvolt = <1500000>;
 455                         regulator-boot-on;
 456                         regulator-always-on;
 457                 };
 458                 dcdc5: regulator-dcdc5 {
 459                         compatible = "ti,tps65218-dcdc5";
 460                         regulator-name = "v1_0bat";
 461                         regulator-min-microvolt = <1000000>;
 462                         regulator-max-microvolt = <1000000>;
 463                 };
 464
 465                 dcdc6: regulator-dcdc6 {
 466                         compatible = "ti,tps65218-dcdc6";
 467                         regulator-name = "v1_8bat";
 468                         regulator-min-microvolt = <1800000>;
 469                         regulator-max-microvolt = <1800000>;
 470                 };
 471
 472                 ldo1: regulator-ldo1 {
 473                         compatible = "ti,tps65218-ldo1";
 474                         regulator-min-microvolt = <1800000>;
 475                         regulator-max-microvolt = <1800000>;
 476                         regulator-boot-on;
 477                         regulator-always-on;
 478                 };
 479         };
 480
 481         ov2659@30 {
 482                 compatible = "ovti,ov2659";
 483                 reg = <0x30>;
 484
 485                 clocks = <&refclk 0>;
 486                 clock-names = "xvclk";
 487
 488                 port {
 489                         ov2659_0: endpoint {
 490                                 remote-endpoint = <&vpfe1_ep>;
 491                                 link-frequencies = /bits/ 64 <70000000>;
 492                         };
 493                 };
 494         };
 495 };
 496
 497 &i2c1 {
 498         status = "okay";
 499         pinctrl-names = "default";
 500         pinctrl-0 = <&i2c1_pins>;
 501         pixcir_ts@5c {
 502                 compatible = "pixcir,pixcir_tangoc";
 503                 pinctrl-names = "default";
 504                 pinctrl-0 = <&pixcir_ts_pins>;
 505                 reg = <0x5c>;
 506                 interrupt-parent = <&gpio3>;
 507                 interrupts = <22 0>;
 508
 509                 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 510
 511                 touchscreen-size-x = <1024>;
 512                 touchscreen-size-y = <600>;
 513         };
 514
 515         ov2659@30 {
 516                 compatible = "ovti,ov2659";
 517                 reg = <0x30>;
 518
 519                 clocks = <&refclk 0>;
 520                 clock-names = "xvclk";
 521
 522                 port {
 523                         ov2659_1: endpoint {
 524                                 remote-endpoint = <&vpfe0_ep>;
 525                                 link-frequencies = /bits/ 64 <70000000>;
 526                         };
 527                 };
 528         };
 529 };
 530
 531 &epwmss0 {
 532         status = "okay";
 533 };
 534
 535 &tscadc {
 536         status = "okay";
 537
 538         adc {
 539                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 540         };
 541 };
 542
 543 &ecap0 {
 544         status = "okay";
 545         pinctrl-names = "default";
 546         pinctrl-0 = <&ecap0_pins>;
 547 };
 548
 549 &gpio0 {
 550         status = "okay";
 551 };
 552
 553 &gpio1 {
 554         status = "okay";
 555 };
 556
 557 &gpio3 {
 558         status = "okay";
 559 };
 560
 561 &gpio4 {
 562         status = "okay";
 563 };
 564
 565 &gpio5 {
 566         status = "okay";
 567         ti,no-reset-on-init;
 568 };
 569
 570 &mmc1 {
 571         status = "okay";
 572         vmmc-supply = <&vmmcsd_fixed>;
 573         bus-width = <4>;
 574         pinctrl-names = "default";
 575         pinctrl-0 = <&mmc1_pins>;
 576         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 577 };
 578
 579 &mmc3 {
 580         /* disable MMC3 as SDIO is not supported in U-Boot */
 581         status = "disabled";
 582         /* these are on the crossbar and are outlined in the
 583            xbar-event-map element */
 584         dmas = <&edma 30
 585                 &edma 31>;
 586         dma-names = "tx", "rx";
 587         vmmc-supply = <&vmmcwl_fixed>;
 588         bus-width = <4>;
 589         pinctrl-names = "default", "sleep";
 590         pinctrl-0 = <&mmc3_pins_default>;
 591         pinctrl-1 = <&mmc3_pins_sleep>;
 592         cap-power-off-card;
 593         keep-power-in-suspend;
 594         ti,non-removable;
 595
 596         #address-cells = <1>;
 597         #size-cells = <0>;
 598         wlcore: wlcore@0 {
 599                 compatible = "ti,wl1835";
 600                 reg = <2>;
 601                 interrupt-parent = <&gpio1>;
 602                 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
 603         };
 604 };
 605
 606 &edma {
 607         ti,edma-xbar-event-map = /bits/ 16 <1 30
 608                                             2 31>;
 609 };
 610
 611 &uart3 {
 612         status = "okay";
 613         pinctrl-names = "default";
 614         pinctrl-0 = <&uart3_pins>;
 615 };
 616
 617 &usb2_phy1 {
 618         status = "okay";
 619 };
 620
 621 &usb1 {
 622         dr_mode = "peripheral";
 623         status = "okay";
 624 };
 625
 626 &usb2_phy2 {
 627         status = "okay";
 628 };
 629
 630 &usb2 {
 631         dr_mode = "host";
 632         status = "okay";
 633 };
 634
 635 &mac {
 636         slaves = <1>;
 637         pinctrl-names = "default", "sleep";
 638         pinctrl-0 = <&cpsw_default>;
 639         pinctrl-1 = <&cpsw_sleep>;
 640         status = "okay";
 641 };
 642
 643 &davinci_mdio {
 644         pinctrl-names = "default", "sleep";
 645         pinctrl-0 = <&davinci_mdio_default>;
 646         pinctrl-1 = <&davinci_mdio_sleep>;
 647         status = "okay";
 648 };
 649
 650 &cpsw_emac0 {
 651         phy_id = <&davinci_mdio>, <0>;
 652         phy-mode = "rgmii";
 653 };
 654
 655 &elm {
 656         status = "okay";
 657 };
 658
 659 &gpmc {
 660         status = "okay";
 661         pinctrl-names = "default";
 662         pinctrl-0 = <&nand_flash_x8>;
 663         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 664         nand@0,0 {
 665                 reg = <0 0 4>;          /* device IO registers */
 666                 ti,nand-ecc-opt = "bch16";
 667                 ti,elm-id = <&elm>;
 668                 nand-bus-width = <8>;
 669                 gpmc,device-width = <1>;
 670                 gpmc,sync-clk-ps = <0>;
 671                 gpmc,cs-on-ns = <0>;
 672                 gpmc,cs-rd-off-ns = <40>;
 673                 gpmc,cs-wr-off-ns = <40>;
 674                 gpmc,adv-on-ns = <0>;
 675                 gpmc,adv-rd-off-ns = <25>;
 676                 gpmc,adv-wr-off-ns = <25>;
 677                 gpmc,we-on-ns = <0>;
 678                 gpmc,we-off-ns = <20>;
 679                 gpmc,oe-on-ns = <3>;
 680                 gpmc,oe-off-ns = <30>;
 681                 gpmc,access-ns = <30>;
 682                 gpmc,rd-cycle-ns = <40>;
 683                 gpmc,wr-cycle-ns = <40>;
 684                 gpmc,wait-pin = <0>;
 685                 gpmc,bus-turnaround-ns = <0>;
 686                 gpmc,cycle2cycle-delay-ns = <0>;
 687                 gpmc,clk-activation-ns = <0>;
 688                 gpmc,wait-monitoring-ns = <0>;
 689                 gpmc,wr-access-ns = <40>;
 690                 gpmc,wr-data-mux-bus-ns = <0>;
 691                 /* MTD partition table */
 692                 /* All SPL-* partitions are sized to minimal length
 693                  * which can be independently programmable. For
 694                  * NAND flash this is equal to size of erase-block */
 695                 #address-cells = <1>;
 696                 #size-cells = <1>;
 697                 partition@0 {
 698                         label = "NAND.SPL";
 699                         reg = <0x00000000 0x00040000>;
 700                 };
 701                 partition@1 {
 702                         label = "NAND.SPL.backup1";
 703                         reg = <0x00040000 0x00040000>;
 704                 };
 705                 partition@2 {
 706                         label = "NAND.SPL.backup2";
 707                         reg = <0x00080000 0x00040000>;
 708                 };
 709                 partition@3 {
 710                         label = "NAND.SPL.backup3";
 711                         reg = <0x000c0000 0x00040000>;
 712                 };
 713                 partition@4 {
 714                         label = "NAND.u-boot-spl-os";
 715                         reg = <0x00100000 0x00080000>;
 716                 };
 717                 partition@5 {
 718                         label = "NAND.u-boot";
 719                         reg = <0x00180000 0x00100000>;
 720                 };
 721                 partition@6 {
 722                         label = "NAND.u-boot-env";
 723                         reg = <0x00280000 0x00040000>;
 724                 };
 725                 partition@7 {
 726                         label = "NAND.u-boot-env.backup1";
 727                         reg = <0x002c0000 0x00040000>;
 728                 };
 729                 partition@8 {
 730                         label = "NAND.kernel";
 731                         reg = <0x00300000 0x00700000>;
 732                 };
 733                 partition@9 {
 734                         label = "NAND.file-system";
 735                         reg = <0x00a00000 0x1f600000>;
 736                 };
 737         };
 738 };
 739
 740 &dss {
 741         status = "ok";
 742
 743         pinctrl-names = "default";
 744         pinctrl-0 = <&dss_pins>;
 745
 746         port {
 747                 dpi_out: endpoint@0 {
 748                         remote-endpoint = <&lcd_in>;
 749                         data-lines = <24>;
 750                 };
 751         };
 752 };
 753
 754 &dcan0 {
 755         pinctrl-names = "default";
 756         pinctrl-0 = <&dcan0_default>;
 757         status = "okay";
 758 };
 759
 760 &dcan1 {
 761         pinctrl-names = "default";
 762         pinctrl-0 = <&dcan1_default>;
 763         status = "okay";
 764 };
 765
 766 &vpfe0 {
 767         status = "okay";
 768         pinctrl-names = "default", "sleep";
 769         pinctrl-0 = <&vpfe0_pins_default>;
 770         pinctrl-1 = <&vpfe0_pins_sleep>;
 771
 772         port {
 773                 vpfe0_ep: endpoint {
 774                         remote-endpoint = <&ov2659_1>;
 775                         ti,am437x-vpfe-interface = <0>;
 776                         bus-width = <8>;
 777                         hsync-active = <0>;
 778                         vsync-active = <0>;
 779                 };
 780         };
 781 };
 782
 783 &vpfe1 {
 784         status = "okay";
 785         pinctrl-names = "default", "sleep";
 786         pinctrl-0 = <&vpfe1_pins_default>;
 787         pinctrl-1 = <&vpfe1_pins_sleep>;
 788
 789         port {
 790                 vpfe1_ep: endpoint {
 791                         remote-endpoint = <&ov2659_0>;
 792                         ti,am437x-vpfe-interface = <0>;
 793                         bus-width = <8>;
 794                         hsync-active = <0>;
 795                         vsync-active = <0>;
 796                 };
 797         };
 798 };