2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
13 #include "am4372.dtsi"
14 #include <dt-bindings/pinctrl/am43xx.h>
15 #include <dt-bindings/pwm/pwm.h>
16 #include <dt-bindings/gpio/gpio.h>
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
31 vmmcsd_fixed: fixedregulator-sd {
32 compatible = "regulator-fixed";
33 regulator-name = "vmmcsd_fixed";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
39 vtt_fixed: fixedregulator-vtt {
40 compatible = "regulator-fixed";
41 regulator-name = "vtt_fixed";
42 regulator-min-microvolt = <1500000>;
43 regulator-max-microvolt = <1500000>;
47 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
50 vmmcwl_fixed: fixedregulator-mmcwl {
51 compatible = "regulator-fixed";
52 regulator-name = "vmmcwl_fixed";
53 regulator-min-microvolt = <1800000>;
54 regulator-max-microvolt = <1800000>;
55 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
60 compatible = "pwm-backlight";
61 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
62 brightness-levels = <0 51 53 56 62 75 101 152 255>;
63 default-brightness-level = <8>;
66 matrix_keypad: matrix_keypad@0 {
67 compatible = "gpio-matrix-keypad";
68 debounce-delay-ms = <5>;
69 col-scan-delay-us = <2>;
71 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
72 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
73 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
75 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
76 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
78 linux,keymap = <0x00000201 /* P1 */
81 0x0101006a /* RIGHT */
83 0x0201006c>; /* DOWN */
87 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
90 pinctrl-names = "default";
91 pinctrl-0 = <&lcd_pins>;
94 * SelLCDorHDMI, LOW to select HDMI. This is not really the
95 * panel's enable GPIO, but we don't have HDMI driver support nor
96 * support to switch between two displays, so using this gpio as
97 * panel's enable should be safe.
99 enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
102 clock-frequency = <33000000>;
105 hfront-porch = <210>;
114 pixelclk-active = <1>;
119 remote-endpoint = <&dpi_out>;
124 /* fixed 12MHz oscillator */
127 compatible = "fixed-clock";
128 clock-frequency = <12000000>;
134 pinctrl-names = "default", "sleep";
135 pinctrl-0 = <&wlan_pins_default>;
136 pinctrl-1 = <&wlan_pins_sleep>;
138 i2c0_pins: i2c0_pins {
139 pinctrl-single,pins = <
140 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
141 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
145 i2c1_pins: i2c1_pins {
146 pinctrl-single,pins = <
147 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
148 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
152 mmc1_pins: pinmux_mmc1_pins {
153 pinctrl-single,pins = <
154 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
158 ecap0_pins: backlight_pins {
159 pinctrl-single,pins = <
160 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
164 pixcir_ts_pins: pixcir_ts_pins {
165 pinctrl-single,pins = <
166 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
170 cpsw_default: cpsw_default {
171 pinctrl-single,pins = <
173 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
174 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
175 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
176 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
177 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
178 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
179 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
180 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
181 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
182 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
183 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
184 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
188 cpsw_sleep: cpsw_sleep {
189 pinctrl-single,pins = <
190 /* Slave 1 reset value */
191 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
192 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
193 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
194 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
195 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
196 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
197 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
198 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
199 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
200 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
201 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
202 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
206 davinci_mdio_default: davinci_mdio_default {
207 pinctrl-single,pins = <
209 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
210 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
214 davinci_mdio_sleep: davinci_mdio_sleep {
215 pinctrl-single,pins = <
216 /* MDIO reset value */
217 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
218 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
222 nand_flash_x8: nand_flash_x8 {
223 pinctrl-single,pins = <
224 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
225 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
226 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
227 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
228 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
229 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
230 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
231 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
232 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
233 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
234 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
235 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
236 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
237 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
238 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
239 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
244 pinctrl-single,pins = <
245 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
246 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
247 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
248 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
249 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
250 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
251 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
252 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
253 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
254 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
255 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
256 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
257 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
258 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
259 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
260 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
261 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
262 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
263 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
264 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
265 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
266 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
267 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
268 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
269 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
270 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
271 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
272 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
278 pinctrl-single,pins = <
279 /* GPIO 5_8 to select LCD / HDMI */
280 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
284 dcan0_default: dcan0_default_pins {
285 pinctrl-single,pins = <
286 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
287 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
291 dcan1_default: dcan1_default_pins {
292 pinctrl-single,pins = <
293 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
294 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
298 vpfe0_pins_default: vpfe0_pins_default {
299 pinctrl-single,pins = <
300 0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
301 0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
302 0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
303 0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
304 0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
305 0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
306 0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
307 0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
308 0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
309 0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
310 0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
311 0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
312 0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
316 vpfe0_pins_sleep: vpfe0_pins_sleep {
317 pinctrl-single,pins = <
318 0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
319 0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
320 0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
321 0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
322 0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
323 0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
324 0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
325 0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
326 0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
327 0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
328 0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
329 0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
330 0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
334 vpfe1_pins_default: vpfe1_pins_default {
335 pinctrl-single,pins = <
336 0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
337 0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
338 0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
339 0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
340 0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
341 0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
342 0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
343 0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
344 0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
345 0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
346 0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
347 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
348 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
352 vpfe1_pins_sleep: vpfe1_pins_sleep {
353 pinctrl-single,pins = <
354 0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
355 0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
356 0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
357 0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
358 0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
359 0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
360 0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
361 0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
362 0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
363 0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
364 0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
365 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
366 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
370 mmc3_pins_default: pinmux_mmc3_pins_default {
371 pinctrl-single,pins = <
372 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
373 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
374 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
375 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
376 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
377 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
381 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
382 pinctrl-single,pins = <
383 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
384 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
385 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
386 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
387 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
388 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
392 wlan_pins_default: pinmux_wlan_pins_default {
393 pinctrl-single,pins = <
394 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
395 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
396 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
400 wlan_pins_sleep: pinmux_wlan_pins_sleep {
401 pinctrl-single,pins = <
402 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
403 0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
404 0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
408 uart3_pins: uart3_pins {
409 pinctrl-single,pins = <
410 0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
411 0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
412 0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
413 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
420 pinctrl-names = "default";
421 pinctrl-0 = <&i2c0_pins>;
422 clock-frequency = <100000>;
424 tps65218: tps65218@24 {
426 compatible = "ti,tps65218";
427 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
428 interrupt-controller;
429 #interrupt-cells = <2>;
431 dcdc1: regulator-dcdc1 {
432 compatible = "ti,tps65218-dcdc1";
433 regulator-name = "vdd_core";
434 regulator-min-microvolt = <912000>;
435 regulator-max-microvolt = <1144000>;
440 dcdc2: regulator-dcdc2 {
441 compatible = "ti,tps65218-dcdc2";
442 regulator-name = "vdd_mpu";
443 regulator-min-microvolt = <912000>;
444 regulator-max-microvolt = <1378000>;
449 dcdc3: regulator-dcdc3 {
450 compatible = "ti,tps65218-dcdc3";
451 regulator-name = "vdcdc3";
452 regulator-min-microvolt = <1500000>;
453 regulator-max-microvolt = <1500000>;
457 dcdc5: regulator-dcdc5 {
458 compatible = "ti,tps65218-dcdc5";
459 regulator-name = "v1_0bat";
460 regulator-min-microvolt = <1000000>;
461 regulator-max-microvolt = <1000000>;
464 dcdc6: regulator-dcdc6 {
465 compatible = "ti,tps65218-dcdc6";
466 regulator-name = "v1_8bat";
467 regulator-min-microvolt = <1800000>;
468 regulator-max-microvolt = <1800000>;
471 ldo1: regulator-ldo1 {
472 compatible = "ti,tps65218-ldo1";
473 regulator-min-microvolt = <1800000>;
474 regulator-max-microvolt = <1800000>;
481 compatible = "ovti,ov2659";
484 clocks = <&refclk 0>;
485 clock-names = "xvclk";
489 remote-endpoint = <&vpfe1_ep>;
490 link-frequencies = /bits/ 64 <70000000>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&i2c1_pins>;
501 compatible = "pixcir,pixcir_tangoc";
502 pinctrl-names = "default";
503 pinctrl-0 = <&pixcir_ts_pins>;
505 interrupt-parent = <&gpio3>;
508 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
510 touchscreen-size-x = <1024>;
511 touchscreen-size-y = <600>;
515 compatible = "ovti,ov2659";
518 clocks = <&refclk 0>;
519 clock-names = "xvclk";
523 remote-endpoint = <&vpfe0_ep>;
524 link-frequencies = /bits/ 64 <70000000>;
538 ti,adc-channels = <0 1 2 3 4 5 6 7>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&ecap0_pins>;
571 vmmc-supply = <&vmmcsd_fixed>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&mmc1_pins>;
575 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
579 /* disable MMC3 as SDIO is not supported in U-Boot */
581 /* these are on the crossbar and are outlined in the
582 xbar-event-map element */
585 dma-names = "tx", "rx";
586 vmmc-supply = <&vmmcwl_fixed>;
588 pinctrl-names = "default", "sleep";
589 pinctrl-0 = <&mmc3_pins_default>;
590 pinctrl-1 = <&mmc3_pins_sleep>;
592 keep-power-in-suspend;
595 #address-cells = <1>;
598 compatible = "ti,wl1835";
600 interrupt-parent = <&gpio1>;
601 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
606 ti,edma-xbar-event-map = /bits/ 16 <1 30
612 pinctrl-names = "default";
613 pinctrl-0 = <&uart3_pins>;
621 dr_mode = "peripheral";
636 pinctrl-names = "default", "sleep";
637 pinctrl-0 = <&cpsw_default>;
638 pinctrl-1 = <&cpsw_sleep>;
643 pinctrl-names = "default", "sleep";
644 pinctrl-0 = <&davinci_mdio_default>;
645 pinctrl-1 = <&davinci_mdio_sleep>;
650 phy_id = <&davinci_mdio>, <0>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&nand_flash_x8>;
662 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
664 reg = <0 0 4>; /* device IO registers */
665 ti,nand-ecc-opt = "bch16";
667 nand-bus-width = <8>;
668 gpmc,device-width = <1>;
669 gpmc,sync-clk-ps = <0>;
671 gpmc,cs-rd-off-ns = <40>;
672 gpmc,cs-wr-off-ns = <40>;
673 gpmc,adv-on-ns = <0>;
674 gpmc,adv-rd-off-ns = <25>;
675 gpmc,adv-wr-off-ns = <25>;
677 gpmc,we-off-ns = <20>;
679 gpmc,oe-off-ns = <30>;
680 gpmc,access-ns = <30>;
681 gpmc,rd-cycle-ns = <40>;
682 gpmc,wr-cycle-ns = <40>;
684 gpmc,bus-turnaround-ns = <0>;
685 gpmc,cycle2cycle-delay-ns = <0>;
686 gpmc,clk-activation-ns = <0>;
687 gpmc,wait-monitoring-ns = <0>;
688 gpmc,wr-access-ns = <40>;
689 gpmc,wr-data-mux-bus-ns = <0>;
690 /* MTD partition table */
691 /* All SPL-* partitions are sized to minimal length
692 * which can be independently programmable. For
693 * NAND flash this is equal to size of erase-block */
694 #address-cells = <1>;
698 reg = <0x00000000 0x00040000>;
701 label = "NAND.SPL.backup1";
702 reg = <0x00040000 0x00040000>;
705 label = "NAND.SPL.backup2";
706 reg = <0x00080000 0x00040000>;
709 label = "NAND.SPL.backup3";
710 reg = <0x000c0000 0x00040000>;
713 label = "NAND.u-boot-spl-os";
714 reg = <0x00100000 0x00080000>;
717 label = "NAND.u-boot";
718 reg = <0x00180000 0x00100000>;
721 label = "NAND.u-boot-env";
722 reg = <0x00280000 0x00040000>;
725 label = "NAND.u-boot-env.backup1";
726 reg = <0x002c0000 0x00040000>;
729 label = "NAND.kernel";
730 reg = <0x00300000 0x00700000>;
733 label = "NAND.file-system";
734 reg = <0x00a00000 0x1f600000>;
742 pinctrl-names = "default";
743 pinctrl-0 = <&dss_pins>;
746 dpi_out: endpoint@0 {
747 remote-endpoint = <&lcd_in>;
754 pinctrl-names = "default";
755 pinctrl-0 = <&dcan0_default>;
760 pinctrl-names = "default";
761 pinctrl-0 = <&dcan1_default>;
767 pinctrl-names = "default", "sleep";
768 pinctrl-0 = <&vpfe0_pins_default>;
769 pinctrl-1 = <&vpfe0_pins_sleep>;
773 remote-endpoint = <&ov2659_1>;
774 ti,am437x-vpfe-interface = <0>;
784 pinctrl-names = "default", "sleep";
785 pinctrl-0 = <&vpfe1_pins_default>;
786 pinctrl-1 = <&vpfe1_pins_sleep>;
790 remote-endpoint = <&ov2659_0>;
791 ti,am437x-vpfe-interface = <0>;