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ARM64: zynqmp: Extend pcie node to support legacy interrupts
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1 /*
2  * Device Tree file for Marvell Armada 375 evaluation board
3  * (DB-88F6720)
4  *
5  *  Copyright (C) 2014 Marvell
6  *
7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9  *
10  * This file is dual-licensed: you can use it either under the terms
11  * of the GPL or the X11 license, at your option. Note that this dual
12  * licensing only applies to this file, and not this project as a
13  * whole.
14  *
15  *  a) This file is free software; you can redistribute it and/or
16  *     modify it under the terms of the GNU General Public License as
17  *     published by the Free Software Foundation; either version 2 of the
18  *     License, or (at your option) any later version.
19  *
20  *     This file is distributed in the hope that it will be useful
21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  *     GNU General Public License for more details.
24  *
25  * Or, alternatively
26  *
27  *  b) Permission is hereby granted, free of charge, to any person
28  *     obtaining a copy of this software and associated documentation
29  *     files (the "Software"), to deal in the Software without
30  *     restriction, including without limitation the rights to use
31  *     copy, modify, merge, publish, distribute, sublicense, and/or
32  *     sell copies of the Software, and to permit persons to whom the
33  *     Software is furnished to do so, subject to the following
34  *     conditions:
35  *
36  *     The above copyright notice and this permission notice shall be
37  *     included in all copies or substantial portions of the Software.
38  *
39  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46  *     OTHER DEALINGS IN THE SOFTWARE.
47  */
48
49 /dts-v1/;
50 #include <dt-bindings/gpio/gpio.h>
51 #include "armada-375.dtsi"
52
53 / {
54         model = "Marvell Armada 375 Development Board";
55         compatible = "marvell,a375-db", "marvell,armada375";
56
57         chosen {
58                 stdout-path = "serial0:115200n8";
59         };
60
61         aliases {
62                 /* So that mvebu u-boot can update the MAC addresses */
63                 ethernet0 = &eth0;
64                 ethernet1 = &eth1;
65                 spi0 = &spi0;
66         };
67
68         memory {
69                 device_type = "memory";
70                 reg = <0x00000000 0x40000000>; /* 1 GB */
71         };
72
73         soc {
74                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
75                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
76                           MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
77                           MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
78
79                 internal-regs {
80                         spi@10600 {
81                                 pinctrl-0 = <&spi0_pins>;
82                                 pinctrl-names = "default";
83                                 /*
84                                  * SPI conflicts with NAND, so we disable it
85                                  * here, and select NAND as the enabled device
86                                  * by default.
87                                  */
88                                 status = "okay";
89                                 u-boot,dm-pre-reloc;
90
91                                 spi-flash@0 {
92                                         u-boot,dm-pre-reloc;
93                                         #address-cells = <1>;
94                                         #size-cells = <1>;
95                                         compatible = "n25q128a13", "jedec,spi-nor";
96                                         reg = <0>; /* Chip select 0 */
97                                         spi-max-frequency = <108000000>;
98                                 };
99                         };
100
101                         i2c@11000 {
102                                 status = "okay";
103                                 clock-frequency = <100000>;
104                                 pinctrl-0 = <&i2c0_pins>;
105                                 pinctrl-names = "default";
106                         };
107
108                         i2c@11100 {
109                                 status = "okay";
110                                 clock-frequency = <100000>;
111                                 pinctrl-0 = <&i2c1_pins>;
112                                 pinctrl-names = "default";
113                         };
114
115                         serial@12000 {
116                                 u-boot,dm-pre-reloc;
117                                 status = "okay";
118                         };
119
120                         pinctrl {
121                                 sdio_st_pins: sdio-st-pins {
122                                         marvell,pins = "mpp44", "mpp45";
123                                         marvell,function = "gpio";
124                                 };
125                         };
126
127                         sata@a0000 {
128                                 status = "okay";
129                                 nr-ports = <2>;
130                         };
131
132                         nand: nand@d0000 {
133                                 pinctrl-0 = <&nand_pins>;
134                                 pinctrl-names = "default";
135                                 status = "okay";
136                                 num-cs = <1>;
137                                 marvell,nand-keep-config;
138                                 marvell,nand-enable-arbiter;
139                                 nand-on-flash-bbt;
140                                 nand-ecc-strength = <4>;
141                                 nand-ecc-step-size = <512>;
142
143                                 partition@0 {
144                                         label = "U-Boot";
145                                         reg = <0 0x800000>;
146                                 };
147                                 partition@800000 {
148                                         label = "Linux";
149                                         reg = <0x800000 0x800000>;
150                                 };
151                                 partition@1000000 {
152                                         label = "Filesystem";
153                                         reg = <0x1000000 0x3f000000>;
154                                 };
155                         };
156
157                         usb@54000 {
158                                 status = "okay";
159                         };
160
161                         usb3@58000 {
162                                 status = "okay";
163                         };
164
165                         mvsdio@d4000 {
166                                 pinctrl-0 = <&sdio_pins &sdio_st_pins>;
167                                 pinctrl-names = "default";
168                                 status = "okay";
169                                 cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
170                                 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
171                         };
172
173                         mdio {
174                                 phy0: ethernet-phy@0 {
175                                         reg = <0>;
176                                 };
177
178                                 phy3: ethernet-phy@3 {
179                                         reg = <3>;
180                                 };
181                         };
182
183                         ethernet@f0000 {
184                                 status = "okay";
185
186                                 eth0@c4000 {
187                                         status = "okay";
188                                         phy = <&phy0>;
189                                         phy-mode = "rgmii-id";
190                                 };
191
192                                 eth1@c5000 {
193                                         status = "okay";
194                                         phy = <&phy3>;
195                                         phy-mode = "gmii";
196                                 };
197                         };
198                 };
199
200                 pcie-controller {
201                         status = "okay";
202                         /*
203                          * The two PCIe units are accessible through
204                          * standard PCIe slots on the board.
205                          */
206                         pcie@1,0 {
207                                 /* Port 0, Lane 0 */
208                                 status = "okay";
209                         };
210                         pcie@2,0 {
211                                 /* Port 1, Lane 0 */
212                                 status = "okay";
213                         };
214                 };
215         };
216 };