2 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 * Copyright (C) 2016 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/comphy/comphy_data.h>
51 model = "Marvell Armada 37xx SoC";
52 compatible = "marvell,armada3700";
53 interrupt-parent = <&gic>;
66 compatible = "arm,cortex-a53", "arm,armv8";
68 enable-method = "psci";
73 compatible = "arm,psci-0.2";
78 compatible = "arm,armv8-timer";
79 interrupts = <GIC_PPI 13
80 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
82 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
84 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
86 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
90 compatible = "simple-bus";
98 compatible = "simple-bus";
99 /* 32M internal register @ 0xd000_0000 */
100 ranges = <0x0 0x0 0xd0000000 0x2000000>;
102 uart0: serial@12000 {
103 compatible = "marvell,armada-3700-uart";
104 reg = <0x12000 0x400>;
105 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
109 pinctrl_nb: pinctrl-nb@13800 {
110 compatible = "marvell,armada3710-nb-pinctrl",
111 "syscon", "simple-mfd";
112 reg = <0x13800 0x100>, <0x13C00 0x20>;
115 gpio-ranges = <&pinctrl_nb 0 0 36>;
118 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
134 pinctrl_sb: pinctrl-sb@18800 {
135 compatible = "marvell,armada3710-sb-pinctrl",
136 "syscon", "simple-mfd";
137 reg = <0x18800 0x100>, <0x18C00 0x20>;
140 gpio-ranges = <&pinctrl_sb 0 0 29>;
143 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
152 compatible = "marvell,armada3700-xhci",
154 reg = <0x58000 0x4000>;
155 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
160 compatible = "marvell,armada3700-ehci";
161 reg = <0x5e000 0x450>;
166 compatible = "marvell,armada-3700-xor";
171 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
174 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
178 sdhci0: sdhci@d0000 {
179 compatible = "marvell,armada-3700-sdhci",
180 "marvell,sdhci-xenon";
186 sdhci1: sdhci@d8000 {
187 compatible = "marvell,armada-3700-sdhci",
188 "marvell,sdhci-xenon";
195 compatible = "marvell,armada-3700-ahci";
196 reg = <0xe0000 0x2000>;
197 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
201 gic: interrupt-controller@1d00000 {
202 compatible = "arm,gic-v3";
203 #interrupt-cells = <3>;
204 interrupt-controller;
205 reg = <0x1d00000 0x10000>, /* GICD */
206 <0x1d40000 0x40000>; /* GICR */
210 compatible = "marvell,armada-3700-neta";
211 reg = <0x30000 0x20>;
216 compatible = "marvell,armada-3700-neta";
217 reg = <0x40000 0x20>;
222 compatible = "marvell,armada-3700-i2c";
223 reg = <0x11000 0x100>;
228 compatible = "marvell,armada-3700-spi";
229 reg = <0x10600 0x50>;
230 #address-cells = <1>;
233 clock-frequency = <160000>;
234 spi-max-frequency = <40000>;
238 pinctl0: pinctl@13830 { /* north bridge */
239 compatible = "marvell,armada-3700-pinctl";
240 bank-name = "armada-3700-nb";
245 pinctl1: pinctl@18830 { /* south bridge */
246 compatible = "marvell,armada-3700-pinctl";
247 bank-name = "armada-3700-sb";
252 comphy: comphy@18300 {
253 compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
254 reg = <0x18300 0x28>,