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rockchip: dts: rk3399: update for spl require driver
[u-boot] / arch / arm / dts / armada-385-amc.dts
1 /*
2  * Device Tree file for Marvell Armada 385 development board
3  * (DB-88F6820-AMC)
4  *
5  * Copyright (C) 2014 Marvell
6  *
7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
8  *
9  * This file is dual-licensed: you can use it either under the terms
10  * of the GPL or the X11 license, at your option. Note that this dual
11  * licensing only applies to this file, and not this project as a
12  * whole.
13  *
14  *  a) This file is licensed under the terms of the GNU General Public
15  *     License version 2.  This program is licensed "as is" without
16  *     any warranty of any kind, whether express or implied.
17  *
18  * Or, alternatively,
19  *
20  *  b) Permission is hereby granted, free of charge, to any person
21  *     obtaining a copy of this software and associated documentation
22  *     files (the "Software"), to deal in the Software without
23  *     restriction, including without limitation the rights to use,
24  *     copy, modify, merge, publish, distribute, sublicense, and/or
25  *     sell copies of the Software, and to permit persons to whom the
26  *     Software is furnished to do so, subject to the following
27  *     conditions:
28  *
29  *     The above copyright notice and this permission notice shall be
30  *     included in all copies or substantial portions of the Software.
31  *
32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39  *     OTHER DEALINGS IN THE SOFTWARE.
40  */
41
42 /dts-v1/;
43 #include "armada-385.dtsi"
44 #include <dt-bindings/gpio/gpio.h>
45
46 / {
47         model = "Marvell Armada 385 AMC";
48         compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
49
50         chosen {
51                 stdout-path = "serial0:115200n8";
52         };
53
54         aliases {
55                 ethernet0 = &eth0;
56                 ethernet1 = &eth1;
57                 spi1 = &spi1;
58         };
59
60         memory {
61                 device_type = "memory";
62                 reg = <0x00000000 0x80000000>; /* 2 GB */
63         };
64
65         soc {
66                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
67                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
68
69                 internal-regs {
70                         i2c@11000 {
71                                 pinctrl-names = "default";
72                                 pinctrl-0 = <&i2c0_pins>;
73                                 status = "okay";
74                         };
75
76                         serial@12000 {
77                                 /*
78                                  * Exported on the micro USB connector CON16
79                                  * through an FTDI
80                                  */
81
82                                 pinctrl-names = "default";
83                                 pinctrl-0 = <&uart0_pins>;
84                                 status = "okay";
85                                 u-boot,dm-pre-reloc;
86                         };
87
88                         ethernet@34000 {
89                                 status = "okay";
90                                 phy = <&phy1>;
91                                 phy-mode = "sgmii";
92                         };
93
94                         usb@58000 {
95                                 status = "okay";
96                         };
97
98                         ethernet@70000 {
99                                 pinctrl-names = "default";
100                                 /*
101                                  * The Reference Clock 0 is used to provide a
102                                  * clock to the PHY
103                                  */
104                                 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
105                                 status = "okay";
106                                 phy = <&phy0>;
107                                 phy-mode = "rgmii-id";
108                         };
109
110
111                         mdio@72004 {
112                                 pinctrl-names = "default";
113                                 pinctrl-0 = <&mdio_pins>;
114
115                                 phy0: ethernet-phy@1 {
116                                         reg = <1>;
117                                 };
118
119                                 phy1: ethernet-phy@0 {
120                                         reg = <0>;
121                                 };
122                         };
123
124                         flash@d0000 {
125                                 status = "okay";
126                                 num-cs = <1>;
127                                 marvell,nand-keep-config;
128                                 marvell,nand-enable-arbiter;
129                                 nand-on-flash-bbt;
130                         };
131                 };
132
133                 pcie-controller {
134                         status = "okay";
135                         pcie@1,0 {
136                                 /* Port 0, Lane 0 */
137                                 status = "okay";
138                         };
139
140                 };
141         };
142 };
143
144 &spi1 {
145         pinctrl-names = "default";
146         pinctrl-0 = <&spi1_pins>;
147         status = "okay";
148         u-boot,dm-pre-reloc;
149
150         spi-flash@0 {
151                 u-boot,dm-pre-reloc;
152                 #address-cells = <1>;
153                 #size-cells = <1>;
154                 compatible = "st,m25p128", "jedec,spi-nor";
155                 reg = <0>; /* Chip select 0 */
156                 spi-max-frequency = <50000000>;
157                 m25p,fast-read;
158         };
159 };
160
161 &refclk {
162         clock-frequency = <20000000>;
163 };