2 * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
4 * Copyright (C) 2015 Russell King
6 * This board is in development; the contents of this file work with
7 * the A1 rev 2.0 of the board, which does not represent final
8 * production board. Things will change, don't expect this file to
9 * remain compatible info the future.
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * version 2 as published by the Free Software Foundation.
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
50 #include <dt-bindings/input/input.h>
51 #include <dt-bindings/gpio/gpio.h>
52 #include "armada-388.dtsi"
55 model = "SolidRun Clearfog A1";
56 compatible = "solidrun,clearfog-a1", "marvell,armada388",
57 "marvell,armada385", "marvell,armada380";
60 /* So that mvebu u-boot can update the MAC addresses */
70 stdout-path = "serial0:115200n8";
74 device_type = "memory";
75 reg = <0x00000000 0x10000000>; /* 256 MB */
78 reg_3p3v: regulator-3p3v {
79 compatible = "regulator-fixed";
80 regulator-name = "3P3V";
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
87 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
88 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
89 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
90 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
94 mac-address = [00 50 43 02 02 02];
105 mac-address = [00 50 43 02 02 03];
106 managed = "in-band-status";
112 mac-address = [00 50 43 02 02 01];
113 pinctrl-0 = <&ge0_rgmii_pins>;
114 pinctrl-names = "default";
115 phy = <&phy_dedicated>;
116 phy-mode = "rgmii-id";
121 /* Is there anything on this? */
122 clock-frequency = <100000>;
123 pinctrl-0 = <&i2c0_pins>;
124 pinctrl-names = "default";
128 * PCA9655 GPIO expander, up to 1MHz clock.
146 expander0: gpio-expander@20 {
148 * This is how it should be:
149 * compatible = "onnn,pca9655",
151 * but you can't do this because of
154 compatible = "nxp,pca9555";
161 gpios = <0 GPIO_ACTIVE_LOW>;
163 line-name = "pcie1.0-clkreq";
167 gpios = <3 GPIO_ACTIVE_LOW>;
169 line-name = "pcie1.0-w-disable";
173 gpios = <4 GPIO_ACTIVE_LOW>;
175 line-name = "pcie2.0-clkreq";
179 gpios = <7 GPIO_ACTIVE_LOW>;
181 line-name = "pcie2.0-w-disable";
185 gpios = <5 GPIO_ACTIVE_LOW>;
187 line-name = "usb3-current-limit";
191 gpios = <6 GPIO_ACTIVE_HIGH>;
193 line-name = "usb3-power";
197 gpios = <11 GPIO_ACTIVE_HIGH>;
199 line-name = "m.2 devslp";
203 /* The MCP3021 is 100kHz clock only */
204 mikrobus_adc: mcp3021@4c {
205 compatible = "microchip,mcp3021";
209 /* Also something at 0x64 */
214 * Routed to SFP, mikrobus, and PCIe.
215 * SFP limits this to 100kHz, and requires
216 * an AT24C01A/02/04 with address pins tied
217 * low, which takes addresses 0x50 and 0x51.
218 * Mikrobus doesn't specify beyond an I2C
220 * PCIe uses ARP to assign addresses, or
223 clock-frequency = <100000>;
224 pinctrl-0 = <&clearfog_i2c1_pins>;
225 pinctrl-names = "default";
230 pinctrl-0 = <&mdio_pins>;
231 pinctrl-names = "default";
233 phy_dedicated: ethernet-phy@0 {
235 * Annoyingly, the marvell phy driver
236 * configures the LED register, rather
237 * than preserving reset-loaded setting.
238 * We undo that rubbish here.
240 marvell,reg-init = <3 16 0 0x101e>;
246 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
247 marvell,pins = "mpp46";
248 marvell,function = "ref";
250 clearfog_dsa0_pins: clearfog-dsa0-pins {
251 marvell,pins = "mpp23", "mpp41";
252 marvell,function = "gpio";
254 clearfog_i2c1_pins: i2c1-pins {
255 /* SFP, PCIe, mSATA, mikrobus */
256 marvell,pins = "mpp26", "mpp27";
257 marvell,function = "i2c1";
259 clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
260 marvell,pins = "mpp20";
261 marvell,function = "gpio";
263 clearfog_sdhci_pins: clearfog-sdhci-pins {
264 marvell,pins = "mpp21", "mpp28",
267 marvell,function = "sd0";
269 clearfog_spi1_cs_pins: spi1-cs-pins {
270 marvell,pins = "mpp55";
271 marvell,function = "spi1";
273 mikro_pins: mikro-pins {
274 /* int: mpp22 rst: mpp29 */
275 marvell,pins = "mpp22", "mpp29";
276 marvell,function = "gpio";
278 mikro_spi_pins: mikro-spi-pins {
279 marvell,pins = "mpp43";
280 marvell,function = "spi1";
282 mikro_uart_pins: mikro-uart-pins {
283 marvell,pins = "mpp24", "mpp25";
284 marvell,function = "ua1";
286 rear_button_pins: rear-button-pins {
287 marvell,pins = "mpp34";
288 marvell,function = "gpio";
294 * If the rtc doesn't work, run "date reset"
312 cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
314 pinctrl-0 = <&clearfog_sdhci_pins
315 &clearfog_sdhci_cd_pins>;
316 pinctrl-names = "default";
323 pinctrl-0 = <&uart0_pins>;
324 pinctrl-names = "default";
331 pinctrl-0 = <&mikro_uart_pins>;
332 pinctrl-names = "default";
342 pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
343 pinctrl-names = "default";
347 #address-cells = <1>;
349 compatible = "w25q32", "jedec,spi-nor", "spi-flash";
350 reg = <0>; /* Chip select 0 */
351 spi-max-frequency = <3000000>;
363 * The two PCIe units are accessible through
364 * the mini-PCIe connectors on the board.
367 /* Port 1, Lane 0. CONN3, nearest power. */
368 reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
372 /* Port 2, Lane 0. CONN2, nearest CPU. */
373 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
380 compatible = "sff,sfp";
382 los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
383 moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
384 sfp,ethernet = <ð2>;
385 tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
386 tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
390 compatible = "marvell,dsa";
391 dsa,ethernet = <ð1>;
392 dsa,mii-bus = <&mdio>;
393 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
394 pinctrl-names = "default";
395 #address-cells = <2>;
399 #address-cells = <1>;
434 /* 88E1512 external phy */
446 compatible = "gpio-keys";
447 pinctrl-0 = <&rear_button_pins>;
448 pinctrl-names = "default";
451 /* The rear SW3 button */
452 label = "Rear Button";
453 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
455 linux,code = <BTN_0>;
461 +#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
462 MPP18: gpio ? (pca9655 int?)
463 MPP19: gpio ? (clkreq?)
464 MPP20: gpio ? (sd0 detect)
466 MPP22: gpio x mikro int
467 MPP23: gpio x switch irq
468 +#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
469 MPP24: ua1:rxd x mikro rx
470 MPP25: ua1:txd x mikro tx
471 MPP26: i2c1:sck x mikro sck
472 MPP27: i2c1:sda x mikro sda
474 MPP29: gpio x mikro rst
475 MPP30: ge1:txd2 ? (config)
476 MPP31: ge1:txd3 ? (config)
477 +#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
478 MPP32: ge1:txctl ? (unused)
479 MPP33: gpio ? (pic_com0)
480 MPP34: gpio x rear button (pic_com1)
481 MPP35: gpio ? (pic_com2)
482 MPP36: gpio ? (unused)
486 +#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
488 MPP41: gpio x switch reset
490 MPP43: spi1:cs2 x mikro cs
491 MPP44: sata3:prsnt ? (unused)
492 MPP45: ref:clk_out0 ?
493 MPP46: ref:clk_out1 x switch clk
495 +#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
503 MPP55: spi1:cs1 x slic
504 +#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
505 MPP56: spi1:mosi x mikro mosi
506 MPP57: spi1:sck x mikro sck
507 MPP58: spi1:miso x mikro miso
508 MPP59: spi1:cs0 x w25q32