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1 /*
2  * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
3  *
4  *  Copyright (C) 2015 Russell King
5  *
6  * This board is in development; the contents of this file work with
7  * the A1 rev 2.0 of the board, which does not represent final
8  * production board.  Things will change, don't expect this file to
9  * remain compatible info the future.
10  *
11  * This file is dual-licensed: you can use it either under the terms
12  * of the GPL or the X11 license, at your option. Note that this dual
13  * licensing only applies to this file, and not this project as a
14  * whole.
15  *
16  *  a) This file is free software; you can redistribute it and/or
17  *     modify it under the terms of the GNU General Public License
18  *     version 2 as published by the Free Software Foundation.
19  *
20  *     This file is distributed in the hope that it will be useful
21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  *     GNU General Public License for more details.
24  *
25  * Or, alternatively
26  *
27  *  b) Permission is hereby granted, free of charge, to any person
28  *     obtaining a copy of this software and associated documentation
29  *     files (the "Software"), to deal in the Software without
30  *     restriction, including without limitation the rights to use
31  *     copy, modify, merge, publish, distribute, sublicense, and/or
32  *     sell copies of the Software, and to permit persons to whom the
33  *     Software is furnished to do so, subject to the following
34  *     conditions:
35  *
36  *     The above copyright notice and this permission notice shall be
37  *     included in all copies or substantial portions of the Software.
38  *
39  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46  *     OTHER DEALINGS IN THE SOFTWARE.
47  */
48
49 /dts-v1/;
50 #include <dt-bindings/input/input.h>
51 #include <dt-bindings/gpio/gpio.h>
52 #include "armada-388.dtsi"
53
54 / {
55         model = "SolidRun Clearfog A1";
56         compatible = "solidrun,clearfog-a1", "marvell,armada388",
57                 "marvell,armada385", "marvell,armada380";
58
59         aliases {
60                 /* So that mvebu u-boot can update the MAC addresses */
61                 ethernet1 = &eth0;
62                 ethernet2 = &eth1;
63                 ethernet3 = &eth2;
64         };
65
66         chosen {
67                 stdout-path = "serial0:115200n8";
68         };
69
70         memory {
71                 device_type = "memory";
72                 reg = <0x00000000 0x10000000>; /* 256 MB */
73         };
74
75         reg_3p3v: regulator-3p3v {
76                 compatible = "regulator-fixed";
77                 regulator-name = "3P3V";
78                 regulator-min-microvolt = <3300000>;
79                 regulator-max-microvolt = <3300000>;
80                 regulator-always-on;
81         };
82
83         soc {
84                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
85                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
86                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
87                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
88
89                 internal-regs {
90                         ethernet@30000 {
91                                 mac-address = [00 50 43 02 02 02];
92                                 phy-mode = "sgmii";
93                                 status = "okay";
94
95                                 fixed-link {
96                                         speed = <1000>;
97                                         full-duplex;
98                                 };
99                         };
100
101                         ethernet@34000 {
102                                 mac-address = [00 50 43 02 02 03];
103                                 managed = "in-band-status";
104                                 phy-mode = "sgmii";
105                                 status = "okay";
106                         };
107
108                         ethernet@70000 {
109                                 mac-address = [00 50 43 02 02 01];
110                                 pinctrl-0 = <&ge0_rgmii_pins>;
111                                 pinctrl-names = "default";
112                                 phy = <&phy_dedicated>;
113                                 phy-mode = "rgmii-id";
114                                 status = "okay";
115                         };
116
117                         i2c@11000 {
118                                 /* Is there anything on this? */
119                                 clock-frequency = <100000>;
120                                 pinctrl-0 = <&i2c0_pins>;
121                                 pinctrl-names = "default";
122                                 status = "okay";
123
124                                 /*
125                                  * PCA9655 GPIO expander, up to 1MHz clock.
126                                  *  0-CON3 CLKREQ#
127                                  *  1-CON3 PERST#
128                                  *  2-CON2 PERST#
129                                  *  3-CON3 W_DISABLE
130                                  *  4-CON2 CLKREQ#
131                                  *  5-USB3 overcurrent
132                                  *  6-USB3 power
133                                  *  7-CON2 W_DISABLE
134                                  *  8-JP4 P1
135                                  *  9-JP4 P4
136                                  * 10-JP4 P5
137                                  * 11-m.2 DEVSLP
138                                  * 12-SFP_LOS
139                                  * 13-SFP_TX_FAULT
140                                  * 14-SFP_TX_DISABLE
141                                  * 15-SFP_MOD_DEF0
142                                  */
143                                 expander0: gpio-expander@20 {
144                                         /*
145                                          * This is how it should be:
146                                          * compatible = "onnn,pca9655",
147                                          *       "nxp,pca9555";
148                                          * but you can't do this because of
149                                          * the way I2C works.
150                                          */
151                                         compatible = "nxp,pca9555";
152                                         gpio-controller;
153                                         #gpio-cells = <2>;
154                                         reg = <0x20>;
155
156                                         pcie1_0_clkreq {
157                                                 gpio-hog;
158                                                 gpios = <0 GPIO_ACTIVE_LOW>;
159                                                 input;
160                                                 line-name = "pcie1.0-clkreq";
161                                         };
162                                         pcie1_0_w_disable {
163                                                 gpio-hog;
164                                                 gpios = <3 GPIO_ACTIVE_LOW>;
165                                                 output-low;
166                                                 line-name = "pcie1.0-w-disable";
167                                         };
168                                         pcie2_0_clkreq {
169                                                 gpio-hog;
170                                                 gpios = <4 GPIO_ACTIVE_LOW>;
171                                                 input;
172                                                 line-name = "pcie2.0-clkreq";
173                                         };
174                                         pcie2_0_w_disable {
175                                                 gpio-hog;
176                                                 gpios = <7 GPIO_ACTIVE_LOW>;
177                                                 output-low;
178                                                 line-name = "pcie2.0-w-disable";
179                                         };
180                                         usb3_ilimit {
181                                                 gpio-hog;
182                                                 gpios = <5 GPIO_ACTIVE_LOW>;
183                                                 input;
184                                                 line-name = "usb3-current-limit";
185                                         };
186                                         usb3_power {
187                                                 gpio-hog;
188                                                 gpios = <6 GPIO_ACTIVE_HIGH>;
189                                                 output-high;
190                                                 line-name = "usb3-power";
191                                         };
192                                         m2_devslp {
193                                                 gpio-hog;
194                                                 gpios = <11 GPIO_ACTIVE_HIGH>;
195                                                 output-low;
196                                                 line-name = "m.2 devslp";
197                                         };
198                                 };
199
200                                 /* The MCP3021 is 100kHz clock only */
201                                 mikrobus_adc: mcp3021@4c {
202                                         compatible = "microchip,mcp3021";
203                                         reg = <0x4c>;
204                                 };
205
206                                 /* Also something at 0x64 */
207                         };
208
209                         i2c@11100 {
210                                 /*
211                                  * Routed to SFP, mikrobus, and PCIe.
212                                  * SFP limits this to 100kHz, and requires
213                                  *  an AT24C01A/02/04 with address pins tied
214                                  *  low, which takes addresses 0x50 and 0x51.
215                                  * Mikrobus doesn't specify beyond an I2C
216                                  *  bus being present.
217                                  * PCIe uses ARP to assign addresses, or
218                                  *  0x63-0x64.
219                                  */
220                                 clock-frequency = <100000>;
221                                 pinctrl-0 = <&clearfog_i2c1_pins>;
222                                 pinctrl-names = "default";
223                                 status = "okay";
224                         };
225
226                         mdio@72004 {
227                                 pinctrl-0 = <&mdio_pins>;
228                                 pinctrl-names = "default";
229
230                                 phy_dedicated: ethernet-phy@0 {
231                                         /*
232                                          * Annoyingly, the marvell phy driver
233                                          * configures the LED register, rather
234                                          * than preserving reset-loaded setting.
235                                          * We undo that rubbish here.
236                                          */
237                                         marvell,reg-init = <3 16 0 0x101e>;
238                                         reg = <0>;
239                                 };
240                         };
241
242                         pinctrl@18000 {
243                                 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
244                                         marvell,pins = "mpp46";
245                                         marvell,function = "ref";
246                                 };
247                                 clearfog_dsa0_pins: clearfog-dsa0-pins {
248                                         marvell,pins = "mpp23", "mpp41";
249                                         marvell,function = "gpio";
250                                 };
251                                 clearfog_i2c1_pins: i2c1-pins {
252                                         /* SFP, PCIe, mSATA, mikrobus */
253                                         marvell,pins = "mpp26", "mpp27";
254                                         marvell,function = "i2c1";
255                                 };
256                                 clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
257                                         marvell,pins = "mpp20";
258                                         marvell,function = "gpio";
259                                 };
260                                 clearfog_sdhci_pins: clearfog-sdhci-pins {
261                                         marvell,pins = "mpp21", "mpp28",
262                                                        "mpp37", "mpp38",
263                                                        "mpp39", "mpp40";
264                                         marvell,function = "sd0";
265                                 };
266                                 clearfog_spi1_cs_pins: spi1-cs-pins {
267                                         marvell,pins = "mpp55";
268                                         marvell,function = "spi1";
269                                 };
270                                 mikro_pins: mikro-pins {
271                                         /* int: mpp22 rst: mpp29 */
272                                         marvell,pins = "mpp22", "mpp29";
273                                         marvell,function = "gpio";
274                                 };
275                                 mikro_spi_pins: mikro-spi-pins {
276                                         marvell,pins = "mpp43";
277                                         marvell,function = "spi1";
278                                 };
279                                 mikro_uart_pins: mikro-uart-pins {
280                                         marvell,pins = "mpp24", "mpp25";
281                                         marvell,function = "ua1";
282                                 };
283                                 rear_button_pins: rear-button-pins {
284                                         marvell,pins = "mpp34";
285                                         marvell,function = "gpio";
286                                 };
287                         };
288
289                         rtc@a3800 {
290                                 /*
291                                  * If the rtc doesn't work, run "date reset"
292                                  * twice in u-boot.
293                                  */
294                                 status = "okay";
295                         };
296
297                         sata@a8000 {
298                                 /* pinctrl? */
299                                 status = "okay";
300                         };
301
302                         sata@e0000 {
303                                 /* pinctrl? */
304                                 status = "okay";
305                         };
306
307                         sdhci@d8000 {
308                                 bus-width = <4>;
309                                 cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
310                                 no-1-8-v;
311                                 pinctrl-0 = <&clearfog_sdhci_pins
312                                              &clearfog_sdhci_cd_pins>;
313                                 pinctrl-names = "default";
314                                 status = "okay";
315                                 vmmc = <&reg_3p3v>;
316                                 wp-inverted;
317                         };
318
319                         serial@12000 {
320                                 pinctrl-0 = <&uart0_pins>;
321                                 pinctrl-names = "default";
322                                 status = "okay";
323                                 u-boot,dm-pre-reloc;
324                         };
325
326                         serial@12100 {
327                                 /* mikrobus uart */
328                                 pinctrl-0 = <&mikro_uart_pins>;
329                                 pinctrl-names = "default";
330                                 status = "okay";
331                         };
332
333                         spi@10680 {
334                                 /*
335                                  * We don't seem to have the W25Q32 on the
336                                  * A1 Rev 2.0 boards, so disable SPI.
337                                  * CS0: W25Q32 (doesn't appear to be present)
338                                  * CS1:
339                                  * CS2: mikrobus
340                                  */
341                                 pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
342                                 pinctrl-names = "default";
343                                 status = "okay";
344
345                                 spi-flash@0 {
346                                         #address-cells = <1>;
347                                         #size-cells = <0>;
348                                         compatible = "w25q32", "jedec,spi-nor";
349                                         reg = <0>; /* Chip select 0 */
350                                         spi-max-frequency = <3000000>;
351                                         status = "disabled";
352                                 };
353                         };
354
355                         usb3@f8000 {
356                                 status = "okay";
357                         };
358                 };
359
360                 pcie-controller {
361                         status = "okay";
362                         /*
363                          * The two PCIe units are accessible through
364                          * the mini-PCIe connectors on the board.
365                          */
366                         pcie@2,0 {
367                                 /* Port 1, Lane 0. CONN3, nearest power. */
368                                 reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
369                                 status = "okay";
370                         };
371                         pcie@3,0 {
372                                 /* Port 2, Lane 0. CONN2, nearest CPU. */
373                                 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
374                                 status = "okay";
375                         };
376                 };
377         };
378
379         sfp: sfp {
380                 compatible = "sff,sfp";
381                 i2c-bus = <&i2c1>;
382                 los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
383                 moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
384                 sfp,ethernet = <&eth2>;
385                 tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
386                 tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
387         };
388
389         dsa@0 {
390                 compatible = "marvell,dsa";
391                 dsa,ethernet = <&eth1>;
392                 dsa,mii-bus = <&mdio>;
393                 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
394                 pinctrl-names = "default";
395                 #address-cells = <2>;
396                 #size-cells = <0>;
397
398                 switch@0 {
399                         #address-cells = <1>;
400                         #size-cells = <0>;
401                         reg = <4 0>;
402
403                         port@0 {
404                                 reg = <0>;
405                                 label = "lan1";
406                         };
407
408                         port@1 {
409                                 reg = <1>;
410                                 label = "lan2";
411                         };
412
413                         port@2 {
414                                 reg = <2>;
415                                 label = "lan3";
416                         };
417
418                         port@3 {
419                                 reg = <3>;
420                                 label = "lan4";
421                         };
422
423                         port@4 {
424                                 reg = <4>;
425                                 label = "lan5";
426                         };
427
428                         port@5 {
429                                 reg = <5>;
430                                 label = "cpu";
431                         };
432
433                         port@6 {
434                                 /* 88E1512 external phy */
435                                 reg = <6>;
436                                 label = "lan6";
437                                 fixed-link {
438                                         speed = <1000>;
439                                         full-duplex;
440                                 };
441                         };
442                 };
443         };
444
445         gpio-keys {
446                 compatible = "gpio-keys";
447                 pinctrl-0 = <&rear_button_pins>;
448                 pinctrl-names = "default";
449
450                 button_0 {
451                         /* The rear SW3 button */
452                         label = "Rear Button";
453                         gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
454                         linux,can-disable;
455                         linux,code = <BTN_0>;
456                 };
457         };
458 };
459
460 /*
461 +#define A38x_CUSTOMER_BOARD_1_MPP16_23         0x00400011
462 MPP18: gpio             ? (pca9655 int?)
463 MPP19: gpio             ? (clkreq?)
464 MPP20: gpio             ? (sd0 detect)
465 MPP21: sd0:cmd          x sd0
466 MPP22: gpio             x mikro int
467 MPP23: gpio             x switch irq
468 +#define A38x_CUSTOMER_BOARD_1_MPP24_31         0x22043333
469 MPP24: ua1:rxd          x mikro rx
470 MPP25: ua1:txd          x mikro tx
471 MPP26: i2c1:sck         x mikro sck
472 MPP27: i2c1:sda         x mikro sda
473 MPP28: sd0:clk          x sd0
474 MPP29: gpio             x mikro rst
475 MPP30: ge1:txd2         ? (config)
476 MPP31: ge1:txd3         ? (config)
477 +#define A38x_CUSTOMER_BOARD_1_MPP32_39         0x44400002
478 MPP32: ge1:txctl        ? (unused)
479 MPP33: gpio             ? (pic_com0)
480 MPP34: gpio             x rear button (pic_com1)
481 MPP35: gpio             ? (pic_com2)
482 MPP36: gpio             ? (unused)
483 MPP37: sd0:d3           x sd0
484 MPP38: sd0:d0           x sd0
485 MPP39: sd0:d1           x sd0
486 +#define A38x_CUSTOMER_BOARD_1_MPP40_47         0x41144004
487 MPP40: sd0:d2           x sd0
488 MPP41: gpio             x switch reset
489 MPP42: gpio             ? sw1-1
490 MPP43: spi1:cs2         x mikro cs
491 MPP44: sata3:prsnt      ? (unused)
492 MPP45: ref:clk_out0     ?
493 MPP46: ref:clk_out1     x switch clk
494 MPP47: 4                ? (unused)
495 +#define A38x_CUSTOMER_BOARD_1_MPP48_55         0x40333333
496 MPP48: tdm:pclk
497 MPP49: tdm:fsync
498 MPP50: tdm:drx
499 MPP51: tdm:dtx
500 MPP52: tdm:int
501 MPP53: tdm:rst
502 MPP54: gpio             ? (pwm)
503 MPP55: spi1:cs1         x slic
504 +#define A38x_CUSTOMER_BOARD_1_MPP56_63         0x00004444
505 MPP56: spi1:mosi        x mikro mosi
506 MPP57: spi1:sck         x mikro sck
507 MPP58: spi1:miso        x mikro miso
508 MPP59: spi1:cs0         x w25q32
509 */