git.sur5r.net Git - u-boot/blob - arch/arm/dts/armada-388-gp.dts

   1 /*
   2  * Device Tree file for Marvell Armada 385 development board
   3  * (RD-88F6820-GP)
   4  *
   5  * Copyright (C) 2014 Marvell
   6  *
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  *
   9  * This file is dual-licensed: you can use it either under the terms
  10  * of the GPL or the X11 license, at your option. Note that this dual
  11  * licensing only applies to this file, and not this project as a
  12  * whole.
  13  *
  14  *  a) This file is licensed under the terms of the GNU General Public
  15  *     License version 2.  This program is licensed "as is" without
  16  *     any warranty of any kind, whether express or implied.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 /dts-v1/;
  43 #include "armada-388.dtsi"
  44 #include <dt-bindings/gpio/gpio.h>
  45
  46 / {
  47         model = "Marvell Armada 385 GP";
  48         compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
  49
  50         chosen {
  51                 stdout-path = "serial0:115200n8";
  52         };
  53
  54         aliases {
  55                 spi0 = &spi0;
  56         };
  57
  58         memory {
  59                 device_type = "memory";
  60                 reg = <0x00000000 0x80000000>; /* 2 GB */
  61         };
  62
  63         soc {
  64                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  65                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  66
  67                 internal-regs {
  68                         spi@10600 {
  69                                 pinctrl-names = "default";
  70                                 pinctrl-0 = <&spi0_pins>;
  71                                 status = "okay";
  72                                 u-boot,dm-pre-reloc;
  73
  74                                 spi-flash@0 {
  75                                         u-boot,dm-pre-reloc;
  76                                         #address-cells = <1>;
  77                                         #size-cells = <1>;
  78                                         compatible = "st,m25p128", "jedec,spi-nor";
  79                                         reg = <0>; /* Chip select 0 */
  80                                         spi-max-frequency = <50000000>;
  81                                         m25p,fast-read;
  82                                 };
  83                         };
  84
  85                         i2c@11000 {
  86                                 pinctrl-names = "default";
  87                                 pinctrl-0 = <&i2c0_pins>;
  88                                 status = "okay";
  89                                 clock-frequency = <100000>;
  90                                 /*
  91                                  * The EEPROM located at adresse 54 is needed
  92                                  * for the boot - DO NOT ERASE IT -
  93                                  */
  94
  95                                 expander0: pca9555@20 {
  96                                         compatible = "nxp,pca9555";
  97                                         pinctrl-names = "default";
  98                                         pinctrl-0 = <&pca0_pins>;
  99                                         interrupt-parent = <&gpio0>;
 100                                         interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
 101                                         gpio-controller;
 102                                         #gpio-cells = <2>;
 103                                         interrupt-controller;
 104                                         #interrupt-cells = <2>;
 105                                         reg = <0x20>;
 106                                 };
 107
 108                                 expander1: pca9555@21 {
 109                                         compatible = "nxp,pca9555";
 110                                         pinctrl-names = "default";
 111                                         interrupt-parent = <&gpio0>;
 112                                         interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
 113                                         gpio-controller;
 114                                         #gpio-cells = <2>;
 115                                         interrupt-controller;
 116                                         #interrupt-cells = <2>;
 117                                         reg = <0x21>;
 118                                 };
 119
 120                         };
 121
 122                         serial@12000 {
 123                                 /*
 124                                  * Exported on the micro USB connector CON16
 125                                  * through an FTDI
 126                                  */
 127
 128                                 pinctrl-names = "default";
 129                                 pinctrl-0 = <&uart0_pins>;
 130                                 status = "okay";
 131                                 u-boot,dm-pre-reloc;
 132                         };
 133
 134                         /* GE1 CON15 */
 135                         ethernet@30000 {
 136                                 pinctrl-names = "default";
 137                                 pinctrl-0 = <&ge1_rgmii_pins>;
 138                                 status = "okay";
 139                                 phy = <&phy1>;
 140                                 phy-mode = "rgmii-id";
 141                         };
 142
 143                         /* CON4 */
 144                         usb@58000 {
 145                                 vcc-supply = <&reg_usb2_0_vbus>;
 146                                 status = "okay";
 147                         };
 148
 149                         /* GE0 CON1 */
 150                         ethernet@70000 {
 151                                 pinctrl-names = "default";
 152                                 /*
 153                                  * The Reference Clock 0 is used to provide a
 154                                  * clock to the PHY
 155                                  */
 156                                 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
 157                                 status = "okay";
 158                                 phy = <&phy0>;
 159                                 phy-mode = "rgmii-id";
 160                         };
 161
 162
 163                         mdio@72004 {
 164                                 pinctrl-names = "default";
 165                                 pinctrl-0 = <&mdio_pins>;
 166
 167                                 phy0: ethernet-phy@1 {
 168                                         reg = <1>;
 169                                 };
 170
 171                                 phy1: ethernet-phy@0 {
 172                                         reg = <0>;
 173                                 };
 174                         };
 175
 176                         sata@a8000 {
 177                                 pinctrl-names = "default";
 178                                 pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
 179                                 status = "okay";
 180                                 #address-cells = <1>;
 181                                 #size-cells = <0>;
 182
 183                                 sata0: sata-port@0 {
 184                                         reg = <0>;
 185                                         target-supply = <&reg_5v_sata0>;
 186                                 };
 187
 188                                 sata1: sata-port@1 {
 189                                         reg = <1>;
 190                                         target-supply = <&reg_5v_sata1>;
 191                                 };
 192                         };
 193
 194                         sata@e0000 {
 195                                 pinctrl-names = "default";
 196                                 pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
 197                                 status = "okay";
 198                                 #address-cells = <1>;
 199                                 #size-cells = <0>;
 200
 201                                 sata2: sata-port@0 {
 202                                         reg = <0>;
 203                                         target-supply = <&reg_5v_sata2>;
 204                                 };
 205
 206                                 sata3: sata-port@1 {
 207                                         reg = <1>;
 208                                         target-supply = <&reg_5v_sata3>;
 209                                 };
 210                         };
 211
 212                         sdhci@d8000 {
 213                                 pinctrl-names = "default";
 214                                 pinctrl-0 = <&sdhci_pins>;
 215                                 cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
 216                                 no-1-8-v;
 217                                 wp-inverted;
 218                                 bus-width = <8>;
 219                                 status = "okay";
 220                         };
 221
 222                         /* CON5 */
 223                         usb3@f0000 {
 224                                 vcc-supply = <&reg_usb2_1_vbus>;
 225                                 status = "okay";
 226                         };
 227
 228                         /* CON7 */
 229                         usb3@f8000 {
 230                                 vcc-supply = <&reg_usb3_vbus>;
 231                                 status = "okay";
 232                         };
 233                 };
 234
 235                 pcie-controller {
 236                         status = "okay";
 237                         /*
 238                          * One PCIe units is accessible through
 239                          * standard PCIe slot on the board.
 240                          */
 241                         pcie@1,0 {
 242                                 /* Port 0, Lane 0 */
 243                                 status = "okay";
 244                         };
 245
 246                         /*
 247                          * The two other PCIe units are accessible
 248                          * through mini PCIe slot on the board.
 249                          */
 250                         pcie@2,0 {
 251                                 /* Port 1, Lane 0 */
 252                                 status = "okay";
 253                         };
 254                         pcie@3,0 {
 255                                 /* Port 2, Lane 0 */
 256                                 status = "okay";
 257                         };
 258                 };
 259
 260                 gpio-fan {
 261                         compatible = "gpio-fan";
 262                         gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
 263                         gpio-fan,speed-map = <   0 0
 264                                               3000 1>;
 265                 };
 266         };
 267
 268         reg_usb3_vbus: usb3-vbus {
 269                 compatible = "regulator-fixed";
 270                 regulator-name = "usb3-vbus";
 271                 regulator-min-microvolt = <5000000>;
 272                 regulator-max-microvolt = <5000000>;
 273                 enable-active-high;
 274                 regulator-always-on;
 275                 gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
 276         };
 277
 278         reg_usb2_0_vbus: v5-vbus0 {
 279                 compatible = "regulator-fixed";
 280                 regulator-name = "v5.0-vbus0";
 281                 regulator-min-microvolt = <5000000>;
 282                 regulator-max-microvolt = <5000000>;
 283                 enable-active-high;
 284                 regulator-always-on;
 285                 gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
 286         };
 287
 288         reg_usb2_1_vbus: v5-vbus1 {
 289                 compatible = "regulator-fixed";
 290                 regulator-name = "v5.0-vbus1";
 291                 regulator-min-microvolt = <5000000>;
 292                 regulator-max-microvolt = <5000000>;
 293                 enable-active-high;
 294                 regulator-always-on;
 295                 gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
 296         };
 297
 298         reg_usb2_1_vbus: v5-vbus1 {
 299                 compatible = "regulator-fixed";
 300                 regulator-name = "v5.0-vbus1";
 301                 regulator-min-microvolt = <5000000>;
 302                 regulator-max-microvolt = <5000000>;
 303                 enable-active-high;
 304                 regulator-always-on;
 305                 gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
 306         };
 307
 308         reg_sata0: pwr-sata0 {
 309                 compatible = "regulator-fixed";
 310                 regulator-name = "pwr_en_sata0";
 311                 enable-active-high;
 312                 regulator-always-on;
 313
 314         };
 315
 316         reg_5v_sata0: v5-sata0 {
 317                 compatible = "regulator-fixed";
 318                 regulator-name = "v5.0-sata0";
 319                 regulator-min-microvolt = <5000000>;
 320                 regulator-max-microvolt = <5000000>;
 321                 regulator-always-on;
 322                 vin-supply = <&reg_sata0>;
 323         };
 324
 325         reg_12v_sata0: v12-sata0 {
 326                 compatible = "regulator-fixed";
 327                 regulator-name = "v12.0-sata0";
 328                 regulator-min-microvolt = <12000000>;
 329                 regulator-max-microvolt = <12000000>;
 330                 regulator-always-on;
 331                 vin-supply = <&reg_sata0>;
 332         };
 333
 334         reg_sata1: pwr-sata1 {
 335                 regulator-name = "pwr_en_sata1";
 336                 compatible = "regulator-fixed";
 337                 regulator-min-microvolt = <12000000>;
 338                 regulator-max-microvolt = <12000000>;
 339                 enable-active-high;
 340                 regulator-always-on;
 341                 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
 342         };
 343
 344         reg_5v_sata1: v5-sata1 {
 345                 compatible = "regulator-fixed";
 346                 regulator-name = "v5.0-sata1";
 347                 regulator-min-microvolt = <5000000>;
 348                 regulator-max-microvolt = <5000000>;
 349                 regulator-always-on;
 350                 vin-supply = <&reg_sata1>;
 351         };
 352
 353         reg_12v_sata1: v12-sata1 {
 354                 compatible = "regulator-fixed";
 355                 regulator-name = "v12.0-sata1";
 356                 regulator-min-microvolt = <12000000>;
 357                 regulator-max-microvolt = <12000000>;
 358                 regulator-always-on;
 359                 vin-supply = <&reg_sata1>;
 360         };
 361
 362         reg_sata2: pwr-sata2 {
 363                 compatible = "regulator-fixed";
 364                 regulator-name = "pwr_en_sata2";
 365                 enable-active-high;
 366                 regulator-always-on;
 367                 gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
 368         };
 369
 370         reg_5v_sata2: v5-sata2 {
 371                 compatible = "regulator-fixed";
 372                 regulator-name = "v5.0-sata2";
 373                 regulator-min-microvolt = <5000000>;
 374                 regulator-max-microvolt = <5000000>;
 375                 regulator-always-on;
 376                 vin-supply = <&reg_sata2>;
 377         };
 378
 379         reg_12v_sata2: v12-sata2 {
 380                 compatible = "regulator-fixed";
 381                 regulator-name = "v12.0-sata2";
 382                 regulator-min-microvolt = <12000000>;
 383                 regulator-max-microvolt = <12000000>;
 384                 regulator-always-on;
 385                 vin-supply = <&reg_sata2>;
 386         };
 387
 388         reg_sata3: pwr-sata3 {
 389                 compatible = "regulator-fixed";
 390                 regulator-name = "pwr_en_sata3";
 391                 enable-active-high;
 392                 regulator-always-on;
 393                 gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
 394         };
 395
 396         reg_5v_sata3: v5-sata3 {
 397                 compatible = "regulator-fixed";
 398                 regulator-name = "v5.0-sata3";
 399                 regulator-min-microvolt = <5000000>;
 400                 regulator-max-microvolt = <5000000>;
 401                 regulator-always-on;
 402                 vin-supply = <&reg_sata3>;
 403         };
 404
 405         reg_12v_sata3: v12-sata3 {
 406                 compatible = "regulator-fixed";
 407                 regulator-name = "v12.0-sata3";
 408                 regulator-min-microvolt = <12000000>;
 409                 regulator-max-microvolt = <12000000>;
 410                 regulator-always-on;
 411                 vin-supply = <&reg_sata3>;
 412         };
 413 };
 414
 415 &pinctrl {
 416         pca0_pins: pca0_pins {
 417                 marvell,pins = "mpp18";
 418                 marvell,function = "gpio";
 419         };
 420 };