git.sur5r.net Git - u-boot/blob - arch/arm/dts/armada-8040-mcbin.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016 Marvell International Ltd.
   4  */
   5
   6 #include "armada-8040.dtsi" /* include SoC device tree */
   7
   8 / {
   9         model = "MACCHIATOBin-8040";
  10         compatible = "marvell,armada8040-mcbin",
  11                      "marvell,armada8040";
  12
  13         chosen {
  14                 stdout-path = "serial0:115200n8";
  15         };
  16
  17         aliases {
  18                 i2c0 = &cpm_i2c0;
  19                 i2c1 = &cpm_i2c1;
  20                 spi0 = &cps_spi1;
  21                 gpio0 = &ap_gpio0;
  22                 gpio1 = &cpm_gpio0;
  23                 gpio2 = &cpm_gpio1;
  24         };
  25
  26         memory@00000000 {
  27                 device_type = "memory";
  28                 reg = <0x0 0x0 0x0 0x80000000>;
  29         };
  30
  31         simple-bus {
  32                 compatible = "simple-bus";
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 reg_usb3h0_vbus: usb3-vbus0 {
  37                         compatible = "regulator-fixed";
  38                         pinctrl-names = "default";
  39                         pinctrl-0 = <&cpm_xhci_vbus_pins>;
  40                         regulator-name = "reg-usb3h0-vbus";
  41                         regulator-min-microvolt = <5000000>;
  42                         regulator-max-microvolt = <5000000>;
  43                         startup-delay-us = <500000>;
  44                         enable-active-high;
  45                         regulator-always-on;
  46                         regulator-boot-on;
  47                         gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
  48                 };
  49         };
  50 };
  51
  52 /* Accessible over the mini-USB CON9 connector on the main board */
  53 &uart0 {
  54         status = "okay";
  55 };
  56
  57 &ap_pinctl {
  58         /*
  59          * MPP Bus:
  60          * eMMC [0-10]
  61          * UART0 [11,19]
  62          */
  63                   /* 0 1 2 3 4 5 6 7 8 9 */
  64         pin-func = < 1 1 1 1 1 1 1 1 1 1
  65                      1 3 0 0 0 0 0 0 0 3 >;
  66 };
  67
  68 /* on-board eMMC */
  69 &ap_sdhci0 {
  70         pinctrl-names = "default";
  71         pinctrl-0 = <&ap_emmc_pins>;
  72         bus-width= <8>;
  73         status = "okay";
  74 };
  75
  76 &cpm_pinctl {
  77         /*
  78          * MPP Bus:
  79          * [0-31] = 0xff: Keep default CP0_shared_pins:
  80          * [11] CLKOUT_MPP_11 (out)
  81          * [23] LINK_RD_IN_CP2CP (in)
  82          * [25] CLKOUT_MPP_25 (out)
  83          * [29] AVS_FB_IN_CP2CP (in)
  84          * [32,34] SMI
  85          * [33]    MSS power down
  86          * [35-38] CP0 I2C1 and I2C0
  87          * [39] MSS CKE Enable
  88          * [40,41] CP0 UART1 TX/RX
  89          * [42,43] XSMI (controls two 10G phys)
  90          * [47] USB VBUS EN
  91          * [48] FAN PWM
  92          * [49] 10G port 1 interrupt
  93          * [50] 10G port 0 interrupt
  94          * [51] 2.5G SFP TX fault
  95          * [52] PCIe reset out
  96          * [53] 2.5G SFP mode
  97          * [54] 2.5G SFP LOS
  98          * [55] Micro SD card detect
  99          * [56-61] Micro SD
 100          * [62] CP1 SFI SFP FAULT
 101          */
 102                 /*   0    1    2    3    4    5    6    7    8    9 */
 103         pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 104                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 105                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 106                      0xff 0    7    0xa  7    2    2    2    2    0xa
 107                      7    7    8    8    0    0    0    0    0    0
 108                      0    0    0    0    0    0    0xe  0xe  0xe  0xe
 109                      0xe  0xe  0 >;
 110
 111         cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
 112                 marvell,pins = < 47 >;
 113                 marvell,function = <0>;
 114         };
 115
 116         cpm_pcie_reset_pins: cpm-pcie-reset-pins {
 117                 marvell,pins = < 52 >;
 118                 marvell,function = <0>;
 119         };
 120 };
 121
 122 /* uSD slot */
 123 &cpm_sdhci0 {
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&cpm_sdhci_pins>;
 126         bus-width= <4>;
 127         status = "okay";
 128 };
 129
 130 /* PCIe x4 */
 131 &cpm_pcie0 {
 132         num-lanes = <4>;
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&cpm_pcie_reset_pins>;
 135         marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */
 136         status = "okay";
 137 };
 138
 139 &cpm_i2c0 {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&cpm_i2c0_pins>;
 142         status = "okay";
 143         clock-frequency = <100000>;
 144 };
 145
 146 &cpm_i2c1 {
 147         pinctrl-names = "default";
 148         pinctrl-0 = <&cpm_i2c1_pins>;
 149         status = "okay";
 150         clock-frequency = <100000>;
 151 };
 152
 153 &cpm_sata0 {
 154         status = "okay";
 155 };
 156
 157 /* uSD slot */
 158 &cpm_sdhci0 {
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&cpm_sdhci_pins>;
 161         bus-width = <4>;
 162         status = "okay";
 163 };
 164
 165 &cpm_comphy {
 166         /*
 167          * CP0 Serdes Configuration:
 168          * Lane 0: PCIe0 (x4)
 169          * Lane 1: PCIe0 (x4)
 170          * Lane 2: PCIe0 (x4)
 171          * Lane 3: PCIe0 (x4)
 172          * Lane 4: SFI (10G)
 173          * Lane 5: SATA1
 174          */
 175         phy0 {
 176                 phy-type = <PHY_TYPE_PEX0>;
 177         };
 178         phy1 {
 179                 phy-type = <PHY_TYPE_PEX0>;
 180         };
 181         phy2 {
 182                 phy-type = <PHY_TYPE_PEX0>;
 183         };
 184         phy3 {
 185                 phy-type = <PHY_TYPE_PEX0>;
 186         };
 187         phy4 {
 188                 phy-type = <PHY_TYPE_SFI>;
 189         };
 190         phy5 {
 191                 phy-type = <PHY_TYPE_SATA1>;
 192         };
 193 };
 194
 195 &cps_sata0 {
 196         status = "okay";
 197 };
 198
 199 &cps_usb3_0 {
 200         vbus-supply = <&reg_usb3h0_vbus>;
 201         status = "okay";
 202 };
 203
 204 &cps_utmi0 {
 205         status = "okay";
 206 };
 207
 208 &cps_pinctl {
 209         /*
 210          * MPP Bus:
 211          * [0-5] TDM
 212          * [6,7] CP1_UART 0
 213          * [8]   CP1 10G SFP LOS
 214          * [9]   CP1 10G PHY RESET
 215          * [10]  CP1 10G SFP TX Disable
 216          * [11]  CP1 10G SFP Mode
 217          * [12]  SPI1 CS1n
 218          * [13]  SPI1 MISO (TDM and SPI ROM shared)
 219          * [14]  SPI1 CS0n
 220          * [15]  SPI1 MOSI (TDM and SPI ROM shared)
 221          * [16]  SPI1 CLK (TDM and SPI ROM shared)
 222          * [24]  CP1 2.5G SFP TX Disable
 223          * [26]  CP0 10G SFP TX Fault
 224          * [27]  CP0 10G SFP Mode
 225          * [28]  CP0 10G SFP LOS
 226          * [29]  CP0 10G SFP TX Disable
 227          * [30]  USB Over current indication
 228          * [31]  10G Port 0 phy reset
 229          * [32-62] = 0xff: Keep default CP1_shared_pins:
 230          */
 231                 /*   0    1    2    3    4    5    6    7    8    9 */
 232         pin-func = < 0x4  0x4  0x4  0x4  0x4  0x4  0x8  0x8  0x0  0x0
 233                      0x0  0x0  0x3  0x3  0x3  0x3  0x3  0xff 0xff 0xff
 234                      0xff 0xff 0xff 0xff 0x0  0xff 0x0  0x0  0x0 0x0
 235                      0x0  0x0  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 236                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 237                      0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
 238                      0xff 0xff 0xff>;
 239 };
 240
 241 &cps_spi1 {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&cps_spi1_pins>;
 244         status = "okay";
 245
 246         spi-flash@0 {
 247                 #address-cells = <1>;
 248                 #size-cells = <1>;
 249                 compatible = "jedec,spi-nor";
 250                 reg = <0>;
 251                 spi-max-frequency = <10000000>;
 252
 253                 partitions {
 254                         compatible = "fixed-partitions";
 255                         #address-cells = <1>;
 256                         #size-cells = <1>;
 257
 258                         partition@0 {
 259                                 label = "U-Boot";
 260                                 reg = <0 0x200000>;
 261                         };
 262                         partition@400000 {
 263                                 label = "Filesystem";
 264                                 reg = <0x200000 0xce0000>;
 265                         };
 266                 };
 267         };
 268 };
 269
 270 &cps_comphy {
 271         /*
 272          * CP1 Serdes Configuration:
 273          * Lane 0: SGMII1
 274          * Lane 1: SATA 0
 275          * Lane 2: USB HOST 0
 276          * Lane 3: SATA1
 277          * Lane 4: SFI (10G)
 278          * Lane 5: SGMII3
 279          */
 280         phy0 {
 281                 phy-type = <PHY_TYPE_SGMII1>;
 282                 phy-speed = <PHY_SPEED_1_25G>;
 283         };
 284         phy1 {
 285                 phy-type = <PHY_TYPE_SATA0>;
 286         };
 287         phy2 {
 288                 phy-type = <PHY_TYPE_USB3_HOST0>;
 289         };
 290         phy3 {
 291                 phy-type = <PHY_TYPE_SATA1>;
 292         };
 293         phy4 {
 294                 phy-type = <PHY_TYPE_SFI>;
 295         };
 296         phy5 {
 297                 phy-type = <PHY_TYPE_SGMII3>;
 298         };
 299 };