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44 * Device Tree file for Marvell Armada CP110 Master.
47 #include <dt-bindings/comphy/comphy_data.h>
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
60 compatible = "simple-bus";
61 interrupt-parent = <&gic>;
62 ranges = <0x0 0x0 0xf2000000 0x2000000>;
64 cpm_syscon0: system-controller@440000 {
65 compatible = "marvell,cp110-system-controller0",
67 reg = <0x440000 0x1000>;
69 core-clock-output-names =
70 "cpm-apll", "cpm-ppv2-core", "cpm-eip",
71 "cpm-core", "cpm-nand-core";
72 gate-clock-output-names =
73 "cpm-audio", "cpm-communit", "cpm-nand",
74 "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
75 "cpm-mg-core", "cpm-xor1", "cpm-xor0",
76 "cpm-gop-dp", "none", "cpm-pcie_x10",
77 "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
78 "cpm-sata", "cpm-sata-usb", "cpm-main",
79 "cpm-sd-mmc", "none", "none",
80 "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
81 "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
84 cpm_pinctl: cpm-pinctl@440000 {
85 compatible = "marvell,mvebu-pinctrl",
86 "marvell,a70x0-pinctrl",
87 "marvell,a80x0-cp0-pinctrl";
89 reg = <0x440000 0x20>;
93 cpm_i2c0_pins: cpm-i2c-pins-0 {
94 marvell,pins = < 37 38 >;
95 marvell,function = <2>;
97 cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
98 marvell,pins = < 44 45 46 47 48 49 50 51
100 marvell,function = <1>;
102 pca0_pins: cpm-pca0_pins {
104 marvell,function = <0>;
106 cpm_sdhci_pins: cpm-sdhi-pins-0 {
107 marvell,pins = < 56 57 58 59 60 61 >;
108 marvell,function = <14>;
110 cpm_spi0_pins: cpm-spi-pins-0 {
111 marvell,pins = < 13 14 15 16 >;
112 marvell,function = <3>;
116 cpm_sata0: sata@540000 {
117 compatible = "marvell,armada-8k-ahci";
118 reg = <0x540000 0x30000>;
119 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&cpm_syscon0 1 15>;
124 cpm_usb3_0: usb3@500000 {
125 compatible = "marvell,armada-8k-xhci",
127 reg = <0x500000 0x4000>;
129 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&cpm_syscon0 1 22>;
134 cpm_usb3_1: usb3@510000 {
135 compatible = "marvell,armada-8k-xhci",
137 reg = <0x510000 0x4000>;
139 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&cpm_syscon0 1 23>;
144 cpm_spi0: spi@700600 {
145 compatible = "marvell,armada-380-spi";
146 reg = <0x700600 0x50>;
147 #address-cells = <0x1>;
150 clocks = <&cpm_syscon0 0 3>;
154 cpm_spi1: spi@700680 {
155 compatible = "marvell,armada-380-spi";
156 reg = <0x700680 0x50>;
157 #address-cells = <1>;
160 clocks = <&cpm_syscon0 1 21>;
164 cpm_i2c0: i2c@701000 {
165 compatible = "marvell,mv78230-i2c";
166 reg = <0x701000 0x20>;
167 #address-cells = <1>;
169 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&cpm_syscon0 1 21>;
174 cpm_i2c1: i2c@701100 {
175 compatible = "marvell,mv78230-i2c";
176 reg = <0x701100 0x20>;
177 #address-cells = <1>;
179 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&cpm_syscon0 1 21>;
184 cpm_comphy: comphy@441000 {
185 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
186 reg = <0x441000 0x8>,
192 cpm_utmi0: utmi@580000 {
193 compatible = "marvell,mvebu-utmi-2.6.0";
194 reg = <0x580000 0x1000>, /* utmi-unit */
195 <0x440420 0x4>, /* usb-cfg */
196 <0x440440 0x4>; /* utmi-cfg */
197 utmi-port = <UTMI_PHY_TO_USB_HOST0>;
201 cpm_utmi1: utmi@581000 {
202 compatible = "marvell,mvebu-utmi-2.6.0";
203 reg = <0x581000 0x1000>, /* utmi-unit */
204 <0x440420 0x4>, /* usb-cfg */
205 <0x440444 0x4>; /* utmi-cfg */
206 utmi-port = <UTMI_PHY_TO_USB_HOST1>;
210 cpm_sdhci0: sdhci@780000 {
211 compatible = "marvell,armada-8k-sdhci";
212 reg = <0x780000 0x300>;
213 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
219 cpm_pcie0: pcie@f2600000 {
220 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
221 reg = <0 0xf2600000 0 0x10000>,
222 <0 0xf6f00000 0 0x80000>;
223 reg-names = "ctrl", "config";
224 #address-cells = <3>;
226 #interrupt-cells = <1>;
230 bus-range = <0 0xff>;
233 <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
234 /* non-prefetchable memory */
235 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
236 interrupt-map-mask = <0 0 0 0>;
237 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cpm_syscon0 1 13>;
244 cpm_pcie1: pcie@f2620000 {
245 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
246 reg = <0 0xf2620000 0 0x10000>,
247 <0 0xf7f00000 0 0x80000>;
248 reg-names = "ctrl", "config";
249 #address-cells = <3>;
251 #interrupt-cells = <1>;
255 bus-range = <0 0xff>;
258 <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
259 /* non-prefetchable memory */
260 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
261 interrupt-map-mask = <0 0 0 0>;
262 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
263 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&cpm_syscon0 1 11>;
270 cpm_pcie2: pcie@f2640000 {
271 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
272 reg = <0 0xf2640000 0 0x10000>,
273 <0 0xf8f00000 0 0x80000>;
274 reg-names = "ctrl", "config";
275 #address-cells = <3>;
277 #interrupt-cells = <1>;
281 bus-range = <0 0xff>;
284 <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
285 /* non-prefetchable memory */
286 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
287 interrupt-map-mask = <0 0 0 0>;
288 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
289 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&cpm_syscon0 1 12>;