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44 * Device Tree file for Marvell Armada CP110 Slave.
47 #include <dt-bindings/comphy/comphy_data.h>
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
60 compatible = "simple-bus";
61 interrupt-parent = <&gic>;
62 ranges = <0x0 0x0 0xf4000000 0x2000000>;
64 cps_syscon0: system-controller@440000 {
65 compatible = "marvell,cp110-system-controller0",
67 reg = <0x440000 0x1000>;
69 core-clock-output-names =
70 "cps-apll", "cps-ppv2-core", "cps-eip",
71 "cps-core", "cps-nand-core";
72 gate-clock-output-names =
73 "cps-audio", "cps-communit", "cps-nand",
74 "cps-ppv2", "cps-sdio", "cps-mg-domain",
75 "cps-mg-core", "cps-xor1", "cps-xor0",
76 "cps-gop-dp", "none", "cps-pcie_x10",
77 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
78 "cps-sata", "cps-sata-usb", "cps-main",
79 "cps-sd-mmc", "none", "none",
80 "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
81 "cps-usb3dev", "cps-eip150", "cps-eip197";
84 cps_pinctl: cps-pinctl@440000 {
85 compatible = "marvell,mvebu-pinctrl",
86 "marvell,a80x0-cp1-pinctrl";
88 reg = <0x440000 0x20>;
92 cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
93 marvell,pins = < 0 1 2 3 4 5 6 7
95 marvell,function = <3>;
97 cps_spi1_pins: cps-spi-pins-1 {
98 marvell,pins = < 13 14 15 16 >;
99 marvell,function = <3>;
103 cps_sata0: sata@540000 {
104 compatible = "marvell,armada-8k-ahci";
105 reg = <0x540000 0x30000>;
106 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&cps_syscon0 1 15>;
111 cps_usb3_0: usb3@500000 {
112 compatible = "marvell,armada-8k-xhci",
114 reg = <0x500000 0x4000>;
116 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&cps_syscon0 1 22>;
121 cps_usb3_1: usb3@510000 {
122 compatible = "marvell,armada-8k-xhci",
124 reg = <0x510000 0x4000>;
126 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&cps_syscon0 1 23>;
131 cps_xor0: xor@6a0000 {
132 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
133 reg = <0x6a0000 0x1000>,
136 msi-parent = <&gic_v2m0>;
137 clocks = <&cps_syscon0 1 8>;
140 cps_xor1: xor@6c0000 {
141 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
142 reg = <0x6c0000 0x1000>,
145 msi-parent = <&gic_v2m0>;
146 clocks = <&cps_syscon0 1 7>;
149 cps_spi0: spi@700600 {
150 compatible = "marvell,armada-380-spi";
151 reg = <0x700600 0x50>;
152 #address-cells = <0x1>;
155 clocks = <&cps_syscon0 0 3>;
159 cps_spi1: spi@700680 {
160 compatible = "marvell,armada-380-spi";
161 reg = <0x700680 0x50>;
162 #address-cells = <1>;
165 clocks = <&cps_syscon0 1 21>;
169 cps_i2c0: i2c@701000 {
170 compatible = "marvell,mv78230-i2c";
171 reg = <0x701000 0x20>;
172 #address-cells = <1>;
174 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&cps_syscon0 1 21>;
179 cps_i2c1: i2c@701100 {
180 compatible = "marvell,mv78230-i2c";
181 reg = <0x701100 0x20>;
182 #address-cells = <1>;
184 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&cps_syscon0 1 21>;
189 cps_comphy: comphy@441000 {
190 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
191 reg = <0x441000 0x8>,
197 cps_utmi0: utmi@580000 {
198 compatible = "marvell,mvebu-utmi-2.6.0";
199 reg = <0x580000 0x1000>, /* utmi-unit */
200 <0x440420 0x4>, /* usb-cfg */
201 <0x440440 0x4>; /* utmi-cfg */
202 utmi-port = <UTMI_PHY_TO_USB_HOST0>;
207 cps_pcie0: pcie@f4600000 {
208 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
209 reg = <0 0xf4600000 0 0x10000>,
210 <0 0xfaf00000 0 0x80000>;
211 reg-names = "ctrl", "config";
212 #address-cells = <3>;
214 #interrupt-cells = <1>;
217 msi-parent = <&gic_v2m0>;
219 bus-range = <0 0xff>;
222 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
223 /* non-prefetchable memory */
224 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
225 interrupt-map-mask = <0 0 0 0>;
226 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
227 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&cps_syscon0 1 13>;
233 cps_pcie1: pcie@f4620000 {
234 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
235 reg = <0 0xf4620000 0 0x10000>,
236 <0 0xfbf00000 0 0x80000>;
237 reg-names = "ctrl", "config";
238 #address-cells = <3>;
240 #interrupt-cells = <1>;
243 msi-parent = <&gic_v2m0>;
245 bus-range = <0 0xff>;
248 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
249 /* non-prefetchable memory */
250 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
251 interrupt-map-mask = <0 0 0 0>;
252 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
253 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&cps_syscon0 1 11>;
260 cps_pcie2: pcie@f4640000 {
261 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
262 reg = <0 0xf4640000 0 0x10000>,
263 <0 0xfcf00000 0 0x80000>;
264 reg-names = "ctrl", "config";
265 #address-cells = <3>;
267 #interrupt-cells = <1>;
270 msi-parent = <&gic_v2m0>;
272 bus-range = <0 0xff>;
275 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
276 /* non-prefetchable memory */
277 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
278 interrupt-map-mask = <0 0 0 0>;
279 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
280 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&cps_syscon0 1 12>;