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[u-boot] / arch / arm / dts / armada-xp-gp.dts
1 /*
2  * Device Tree file for Marvell Armada XP development board
3  * (DB-MV784MP-GP)
4  *
5  * Copyright (C) 2013-2014 Marvell
6  *
7  * Lior Amsalem <alior@marvell.com>
8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10  *
11  * This file is dual-licensed: you can use it either under the terms
12  * of the GPL or the X11 license, at your option. Note that this dual
13  * licensing only applies to this file, and not this project as a
14  * whole.
15  *
16  *  a) This file is free software; you can redistribute it and/or
17  *     modify it under the terms of the GNU General Public License as
18  *     published by the Free Software Foundation; either version 2 of the
19  *     License, or (at your option) any later version.
20  *
21  *     This file is distributed in the hope that it will be useful
22  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
23  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24  *     GNU General Public License for more details.
25  *
26  * Or, alternatively
27  *
28  *  b) Permission is hereby granted, free of charge, to any person
29  *     obtaining a copy of this software and associated documentation
30  *     files (the "Software"), to deal in the Software without
31  *     restriction, including without limitation the rights to use
32  *     copy, modify, merge, publish, distribute, sublicense, and/or
33  *     sell copies of the Software, and to permit persons to whom the
34  *     Software is furnished to do so, subject to the following
35  *     conditions:
36  *
37  *     The above copyright notice and this permission notice shall be
38  *     included in all copies or substantial portions of the Software.
39  *
40  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47  *     OTHER DEALINGS IN THE SOFTWARE.
48  *
49  * Note: this Device Tree assumes that the bootloader has remapped the
50  * internal registers to 0xf1000000 (instead of the default
51  * 0xd0000000). The 0xf1000000 is the default used by the recent,
52  * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
53  * boards were delivered with an older version of the bootloader that
54  * left internal registers mapped at 0xd0000000. If you are in this
55  * situation, you should either update your bootloader (preferred
56  * solution) or the below Device Tree should be adjusted.
57  */
58
59 /dts-v1/;
60 #include <dt-bindings/gpio/gpio.h>
61 #include "armada-xp-mv78460.dtsi"
62
63 / {
64         model = "Marvell Armada XP Development Board DB-MV784MP-GP";
65         compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
66
67         chosen {
68                 stdout-path = "serial0:115200n8";
69         };
70
71         aliases {
72                 spi0 = &spi0;
73         };
74
75         memory {
76                 device_type = "memory";
77                 /*
78                  * 8 GB of plug-in RAM modules by default.The amount
79                  * of memory available can be changed by the
80                  * bootloader according the size of the module
81                  * actually plugged. However, memory between
82                  * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
83                  * the address range used for I/O (internal registers,
84                  * MBus windows).
85                  */
86                 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
87                       <0x00000001 0x00000000 0x00000001 0x00000000>;
88         };
89
90         cpus {
91                 pm_pic {
92                         ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
93                                      <&gpio0 17 GPIO_ACTIVE_LOW>,
94                                      <&gpio0 18 GPIO_ACTIVE_LOW>;
95                 };
96         };
97
98         soc {
99                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
100                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
101                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
102
103                 devbus-bootcs {
104                         status = "okay";
105
106                         /* Device Bus parameters are required */
107
108                         /* Read parameters */
109                         devbus,bus-width    = <16>;
110                         devbus,turn-off-ps  = <60000>;
111                         devbus,badr-skew-ps = <0>;
112                         devbus,acc-first-ps = <124000>;
113                         devbus,acc-next-ps  = <248000>;
114                         devbus,rd-setup-ps  = <0>;
115                         devbus,rd-hold-ps   = <0>;
116
117                         /* Write parameters */
118                         devbus,sync-enable = <0>;
119                         devbus,wr-high-ps  = <60000>;
120                         devbus,wr-low-ps   = <60000>;
121                         devbus,ale-wr-ps   = <60000>;
122
123                         /* NOR 16 MiB */
124                         nor@0 {
125                                 compatible = "cfi-flash";
126                                 reg = <0 0x1000000>;
127                                 bank-width = <2>;
128                         };
129                 };
130
131                 pcie-controller {
132                         status = "okay";
133
134                         /*
135                          * The 3 slots are physically present as
136                          * standard PCIe slots on the board.
137                          */
138                         pcie@1,0 {
139                                 /* Port 0, Lane 0 */
140                                 status = "okay";
141                         };
142                         pcie@9,0 {
143                                 /* Port 2, Lane 0 */
144                                 status = "okay";
145                         };
146                         pcie@10,0 {
147                                 /* Port 3, Lane 0 */
148                                 status = "okay";
149                         };
150                 };
151
152                 internal-regs {
153                         serial@12000 {
154                                 status = "okay";
155                                 u-boot,dm-pre-reloc;
156                         };
157                         serial@12100 {
158                                 status = "okay";
159                         };
160                         serial@12200 {
161                                 status = "okay";
162                         };
163                         serial@12300 {
164                                 status = "okay";
165                         };
166                         pinctrl {
167                                 pinctrl-0 = <&pic_pins>;
168                                 pinctrl-names = "default";
169                                 pic_pins: pic-pins-0 {
170                                         marvell,pins = "mpp16", "mpp17",
171                                                        "mpp18";
172                                         marvell,function = "gpio";
173                                 };
174                         };
175                         sata@a0000 {
176                                 nr-ports = <2>;
177                                 status = "okay";
178                         };
179
180                         mdio {
181                                 phy0: ethernet-phy@0 {
182                                         reg = <16>;
183                                 };
184
185                                 phy1: ethernet-phy@1 {
186                                         reg = <17>;
187                                 };
188
189                                 phy2: ethernet-phy@2 {
190                                         reg = <18>;
191                                 };
192
193                                 phy3: ethernet-phy@3 {
194                                         reg = <19>;
195                                 };
196                         };
197
198                         ethernet@70000 {
199                                 status = "okay";
200                                 phy = <&phy0>;
201                                 phy-mode = "qsgmii";
202                         };
203                         ethernet@74000 {
204                                 status = "okay";
205                                 phy = <&phy1>;
206                                 phy-mode = "qsgmii";
207                         };
208                         ethernet@30000 {
209                                 status = "okay";
210                                 phy = <&phy2>;
211                                 phy-mode = "qsgmii";
212                         };
213                         ethernet@34000 {
214                                 status = "okay";
215                                 phy = <&phy3>;
216                                 phy-mode = "qsgmii";
217                         };
218
219                         /* Front-side USB slot */
220                         usb@50000 {
221                                 status = "okay";
222                         };
223
224                         /* Back-side USB slot */
225                         usb@51000 {
226                                 status = "okay";
227                         };
228
229                         spi0: spi@10600 {
230                                 status = "okay";
231                                 u-boot,dm-pre-reloc;
232
233                                 spi-flash@0 {
234                                         u-boot,dm-pre-reloc;
235                                         #address-cells = <1>;
236                                         #size-cells = <1>;
237                                         compatible = "n25q128a13", "jedec,spi-nor";
238                                         reg = <0>; /* Chip select 0 */
239                                         spi-max-frequency = <108000000>;
240                                 };
241                         };
242
243                         nand@d0000 {
244                                 status = "okay";
245                                 num-cs = <1>;
246                                 marvell,nand-keep-config;
247                                 marvell,nand-enable-arbiter;
248                                 nand-on-flash-bbt;
249                         };
250                 };
251         };
252 };