]> git.sur5r.net Git - u-boot/blob - arch/arm/dts/armada-xp-maxbcm.dts
rockchip: dts: tinker: add usb host power supply node
[u-boot] / arch / arm / dts / armada-xp-maxbcm.dts
1 /*
2  * Device Tree file for Marvell Armada XP maxbcm board
3  *
4  * Copyright (C) 2013-2014 Marvell
5  *
6  * Lior Amsalem <alior@marvell.com>
7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9  *
10  * This file is dual-licensed: you can use it either under the terms
11  * of the GPL or the X11 license, at your option. Note that this dual
12  * licensing only applies to this file, and not this project as a
13  * whole.
14  *
15  *  a) This file is free software; you can redistribute it and/or
16  *     modify it under the terms of the GNU General Public License as
17  *     published by the Free Software Foundation; either version 2 of the
18  *     License, or (at your option) any later version.
19  *
20  *     This file is distributed in the hope that it will be useful
21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  *     GNU General Public License for more details.
24  *
25  * Or, alternatively
26  *
27  *  b) Permission is hereby granted, free of charge, to any person
28  *     obtaining a copy of this software and associated documentation
29  *     files (the "Software"), to deal in the Software without
30  *     restriction, including without limitation the rights to use
31  *     copy, modify, merge, publish, distribute, sublicense, and/or
32  *     sell copies of the Software, and to permit persons to whom the
33  *     Software is furnished to do so, subject to the following
34  *     conditions:
35  *
36  *     The above copyright notice and this permission notice shall be
37  *     included in all copies or substantial portions of the Software.
38  *
39  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46  *     OTHER DEALINGS IN THE SOFTWARE.
47  *
48  * Note: this Device Tree assumes that the bootloader has remapped the
49  * internal registers to 0xf1000000 (instead of the default
50  * 0xd0000000). The 0xf1000000 is the default used by the recent,
51  * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
52  * boards were delivered with an older version of the bootloader that
53  * left internal registers mapped at 0xd0000000. If you are in this
54  * situation, you should either update your bootloader (preferred
55  * solution) or the below Device Tree should be adjusted.
56  */
57
58 /dts-v1/;
59 #include <dt-bindings/gpio/gpio.h>
60 #include "armada-xp-mv78460.dtsi"
61
62 / {
63         model = "Marvell Armada XP MAXBCM";
64         compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
65
66         chosen {
67                 stdout-path = "serial0:115200n8";
68         };
69
70         aliases {
71                 spi0 = &spi0;
72         };
73
74         memory {
75                 device_type = "memory";
76                 /*
77                  * 8 GB of plug-in RAM modules by default.The amount
78                  * of memory available can be changed by the
79                  * bootloader according the size of the module
80                  * actually plugged. However, memory between
81                  * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
82                  * the address range used for I/O (internal registers,
83                  * MBus windows).
84                  */
85                 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
86                       <0x00000001 0x00000000 0x00000001 0x00000000>;
87         };
88
89         cpus {
90                 pm_pic {
91                         ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
92                                      <&gpio0 17 GPIO_ACTIVE_LOW>,
93                                      <&gpio0 18 GPIO_ACTIVE_LOW>;
94                 };
95         };
96
97         soc {
98                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
99                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
100                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
101
102                 devbus-bootcs {
103                         status = "okay";
104
105                         /* Device Bus parameters are required */
106
107                         /* Read parameters */
108                         devbus,bus-width    = <16>;
109                         devbus,turn-off-ps  = <60000>;
110                         devbus,badr-skew-ps = <0>;
111                         devbus,acc-first-ps = <124000>;
112                         devbus,acc-next-ps  = <248000>;
113                         devbus,rd-setup-ps  = <0>;
114                         devbus,rd-hold-ps   = <0>;
115
116                         /* Write parameters */
117                         devbus,sync-enable = <0>;
118                         devbus,wr-high-ps  = <60000>;
119                         devbus,wr-low-ps   = <60000>;
120                         devbus,ale-wr-ps   = <60000>;
121
122                         /* NOR 16 MiB */
123                         nor@0 {
124                                 compatible = "cfi-flash";
125                                 reg = <0 0x1000000>;
126                                 bank-width = <2>;
127                         };
128                 };
129
130                 pcie-controller {
131                         status = "okay";
132
133                         /*
134                          * The 3 slots are physically present as
135                          * standard PCIe slots on the board.
136                          */
137                         pcie@1,0 {
138                                 /* Port 0, Lane 0 */
139                                 status = "okay";
140                         };
141                         pcie@9,0 {
142                                 /* Port 2, Lane 0 */
143                                 status = "okay";
144                         };
145                         pcie@10,0 {
146                                 /* Port 3, Lane 0 */
147                                 status = "okay";
148                         };
149                 };
150
151                 internal-regs {
152                         serial@12000 {
153                                 status = "okay";
154                                 u-boot,dm-pre-reloc;
155                         };
156                         serial@12100 {
157                                 status = "okay";
158                         };
159                         serial@12200 {
160                                 status = "okay";
161                         };
162                         serial@12300 {
163                                 status = "okay";
164                         };
165                         pinctrl {
166                                 pinctrl-0 = <&pic_pins>;
167                                 pinctrl-names = "default";
168                                 pic_pins: pic-pins-0 {
169                                         marvell,pins = "mpp16", "mpp17",
170                                                        "mpp18";
171                                         marvell,function = "gpio";
172                                 };
173                         };
174                         sata@a0000 {
175                                 nr-ports = <2>;
176                                 status = "okay";
177                         };
178
179                         mdio {
180                                 phy0: ethernet-phy@0 {
181                                         reg = <0>;
182                                 };
183
184                                 phy1: ethernet-phy@1 {
185                                         reg = <1>;
186                                 };
187
188                                 phy2: ethernet-phy@2 {
189                                         reg = <2>;
190                                 };
191
192                                 phy3: ethernet-phy@3 {
193                                         reg = <3>;
194                                 };
195                         };
196
197                         ethernet@70000 {
198                                 status = "okay";
199                                 phy = <&phy0>;
200                                 phy-mode = "sgmii";
201                         };
202                         ethernet@74000 {
203                                 status = "okay";
204                                 phy = <&phy1>;
205                                 phy-mode = "sgmii";
206                         };
207                         ethernet@30000 {
208                                 status = "okay";
209                                 phy = <&phy2>;
210                                 phy-mode = "sgmii";
211                         };
212                         ethernet@34000 {
213                                 status = "okay";
214                                 phy = <&phy3>;
215                                 phy-mode = "sgmii";
216                         };
217
218                         /* Front-side USB slot */
219                         usb@50000 {
220                                 status = "okay";
221                         };
222
223                         /* Back-side USB slot */
224                         usb@51000 {
225                                 status = "okay";
226                         };
227
228                         spi0: spi@10600 {
229                                 status = "okay";
230
231                                 spi-flash@0 {
232                                         #address-cells = <1>;
233                                         #size-cells = <1>;
234                                         compatible = "n25q128a13", "jedec,spi-nor";
235                                         reg = <0>; /* Chip select 0 */
236                                         spi-max-frequency = <108000000>;
237                                 };
238                         };
239
240                         nand@d0000 {
241                                 status = "okay";
242                                 num-cs = <1>;
243                                 marvell,nand-keep-config;
244                                 marvell,nand-enable-arbiter;
245                                 nand-on-flash-bbt;
246                         };
247                 };
248         };
249 };