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1 /*
2  * Device Tree Include file for Marvell Armada XP family SoC
3  *
4  * Copyright (C) 2012 Marvell
5  *
6  * Lior Amsalem <alior@marvell.com>
7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9  * Ben Dooks <ben.dooks@codethink.co.uk>
10  *
11  * This file is dual-licensed: you can use it either under the terms
12  * of the GPL or the X11 license, at your option. Note that this dual
13  * licensing only applies to this file, and not this project as a
14  * whole.
15  *
16  *  a) This file is free software; you can redistribute it and/or
17  *     modify it under the terms of the GNU General Public License as
18  *     published by the Free Software Foundation; either version 2 of the
19  *     License, or (at your option) any later version.
20  *
21  *     This file is distributed in the hope that it will be useful
22  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
23  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24  *     GNU General Public License for more details.
25  *
26  * Or, alternatively
27  *
28  *  b) Permission is hereby granted, free of charge, to any person
29  *     obtaining a copy of this software and associated documentation
30  *     files (the "Software"), to deal in the Software without
31  *     restriction, including without limitation the rights to use
32  *     copy, modify, merge, publish, distribute, sublicense, and/or
33  *     sell copies of the Software, and to permit persons to whom the
34  *     Software is furnished to do so, subject to the following
35  *     conditions:
36  *
37  *     The above copyright notice and this permission notice shall be
38  *     included in all copies or substantial portions of the Software.
39  *
40  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47  *     OTHER DEALINGS IN THE SOFTWARE.
48  *
49  * Contains definitions specific to the Armada XP SoC that are not
50  * common to all Armada SoCs.
51  */
52
53 #include "armada-370-xp.dtsi"
54
55 / {
56         model = "Marvell Armada XP family SoC";
57         compatible = "marvell,armadaxp", "marvell,armada-370-xp";
58
59         aliases {
60                 serial2 = &uart2;
61                 serial3 = &uart3;
62         };
63
64         soc {
65                 compatible = "marvell,armadaxp-mbus", "simple-bus";
66                 u-boot,dm-pre-reloc;
67
68                 bootrom {
69                         compatible = "marvell,bootrom";
70                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
71                 };
72
73                 internal-regs {
74                         sdramc@1400 {
75                                 compatible = "marvell,armada-xp-sdram-controller";
76                                 reg = <0x1400 0x500>;
77                         };
78
79                         L2: l2-cache {
80                                 compatible = "marvell,aurora-system-cache";
81                                 reg = <0x08000 0x1000>;
82                                 cache-id-part = <0x100>;
83                                 cache-level = <2>;
84                                 cache-unified;
85                                 wt-override;
86                         };
87
88                         spi0: spi@10600 {
89                                 compatible = "marvell,armada-xp-spi",
90                                                 "marvell,orion-spi";
91                                 pinctrl-0 = <&spi0_pins>;
92                                 pinctrl-names = "default";
93                         };
94
95                         spi1: spi@10680 {
96                                 compatible = "marvell,armada-xp-spi",
97                                                 "marvell,orion-spi";
98                         };
99
100
101                         i2c0: i2c@11000 {
102                                 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
103                                 reg = <0x11000 0x100>;
104                         };
105
106                         i2c1: i2c@11100 {
107                                 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
108                                 reg = <0x11100 0x100>;
109                         };
110
111                         uart2: serial@12200 {
112                                 compatible = "snps,dw-apb-uart";
113                                 pinctrl-0 = <&uart2_pins>;
114                                 pinctrl-names = "default";
115                                 reg = <0x12200 0x100>;
116                                 reg-shift = <2>;
117                                 interrupts = <43>;
118                                 reg-io-width = <1>;
119                                 clocks = <&coreclk 0>;
120                                 status = "disabled";
121                         };
122
123                         uart3: serial@12300 {
124                                 compatible = "snps,dw-apb-uart";
125                                 pinctrl-0 = <&uart3_pins>;
126                                 pinctrl-names = "default";
127                                 reg = <0x12300 0x100>;
128                                 reg-shift = <2>;
129                                 interrupts = <44>;
130                                 reg-io-width = <1>;
131                                 clocks = <&coreclk 0>;
132                                 status = "disabled";
133                         };
134
135                         system-controller@18200 {
136                                 compatible = "marvell,armada-370-xp-system-controller";
137                                 reg = <0x18200 0x500>;
138                         };
139
140                         gateclk: clock-gating-control@18220 {
141                                 compatible = "marvell,armada-xp-gating-clock";
142                                 reg = <0x18220 0x4>;
143                                 clocks = <&coreclk 0>;
144                                 #clock-cells = <1>;
145                         };
146
147                         coreclk: mvebu-sar@18230 {
148                                 compatible = "marvell,armada-xp-core-clock";
149                                 reg = <0x18230 0x08>;
150                                 #clock-cells = <1>;
151                         };
152
153                         thermal@182b0 {
154                                 compatible = "marvell,armadaxp-thermal";
155                                 reg = <0x182b0 0x4
156                                         0x184d0 0x4>;
157                                 status = "okay";
158                         };
159
160                         cpuclk: clock-complex@18700 {
161                                 #clock-cells = <1>;
162                                 compatible = "marvell,armada-xp-cpu-clock";
163                                 reg = <0x18700 0x24>, <0x1c054 0x10>;
164                                 clocks = <&coreclk 1>;
165                         };
166
167                         interrupt-controller@20a00 {
168                               reg = <0x20a00 0x2d0>, <0x21070 0x58>;
169                         };
170
171                         timer@20300 {
172                                 compatible = "marvell,armada-xp-timer";
173                                 clocks = <&coreclk 2>, <&refclk>;
174                                 clock-names = "nbclk", "fixed";
175                         };
176
177                         watchdog@20300 {
178                                 compatible = "marvell,armada-xp-wdt";
179                                 clocks = <&coreclk 2>, <&refclk>;
180                                 clock-names = "nbclk", "fixed";
181                         };
182
183                         cpurst@20800 {
184                                 compatible = "marvell,armada-370-cpu-reset";
185                                 reg = <0x20800 0x20>;
186                         };
187
188                         eth2: ethernet@30000 {
189                                 compatible = "marvell,armada-xp-neta";
190                                 reg = <0x30000 0x4000>;
191                                 interrupts = <12>;
192                                 clocks = <&gateclk 2>;
193                                 status = "disabled";
194                         };
195
196                         usb@50000 {
197                                 clocks = <&gateclk 18>;
198                         };
199
200                         usb@51000 {
201                                 clocks = <&gateclk 19>;
202                         };
203
204                         usb@52000 {
205                                 compatible = "marvell,orion-ehci";
206                                 reg = <0x52000 0x500>;
207                                 interrupts = <47>;
208                                 clocks = <&gateclk 20>;
209                                 status = "disabled";
210                         };
211
212                         xor@60900 {
213                                 compatible = "marvell,orion-xor";
214                                 reg = <0x60900 0x100
215                                        0x60b00 0x100>;
216                                 clocks = <&gateclk 22>;
217                                 status = "okay";
218
219                                 xor10 {
220                                         interrupts = <51>;
221                                         dmacap,memcpy;
222                                         dmacap,xor;
223                                 };
224                                 xor11 {
225                                         interrupts = <52>;
226                                         dmacap,memcpy;
227                                         dmacap,xor;
228                                         dmacap,memset;
229                                 };
230                         };
231
232                         ethernet@70000 {
233                                 compatible = "marvell,armada-xp-neta";
234                         };
235
236                         ethernet@74000 {
237                                 compatible = "marvell,armada-xp-neta";
238                         };
239
240                         xor@f0900 {
241                                 compatible = "marvell,orion-xor";
242                                 reg = <0xF0900 0x100
243                                        0xF0B00 0x100>;
244                                 clocks = <&gateclk 28>;
245                                 status = "okay";
246
247                                 xor00 {
248                                         interrupts = <94>;
249                                         dmacap,memcpy;
250                                         dmacap,xor;
251                                 };
252                                 xor01 {
253                                         interrupts = <95>;
254                                         dmacap,memcpy;
255                                         dmacap,xor;
256                                         dmacap,memset;
257                                 };
258                         };
259                 };
260         };
261
262         clocks {
263                 /* 25 MHz reference crystal */
264                 refclk: oscillator {
265                         compatible = "fixed-clock";
266                         #clock-cells = <0>;
267                         clock-frequency = <25000000>;
268                 };
269         };
270 };
271
272 &pinctrl {
273         ge0_gmii_pins: ge0-gmii-pins {
274                 marvell,pins =
275                      "mpp0",  "mpp1",  "mpp2",  "mpp3",
276                      "mpp4",  "mpp5",  "mpp6",  "mpp7",
277                      "mpp8",  "mpp9",  "mpp10", "mpp11",
278                      "mpp12", "mpp13", "mpp14", "mpp15",
279                      "mpp16", "mpp17", "mpp18", "mpp19",
280                      "mpp20", "mpp21", "mpp22", "mpp23";
281                 marvell,function = "ge0";
282         };
283
284         ge0_rgmii_pins: ge0-rgmii-pins {
285                 marvell,pins =
286                      "mpp0", "mpp1", "mpp2", "mpp3",
287                      "mpp4", "mpp5", "mpp6", "mpp7",
288                      "mpp8", "mpp9", "mpp10", "mpp11";
289                 marvell,function = "ge0";
290         };
291
292         ge1_rgmii_pins: ge1-rgmii-pins {
293                 marvell,pins =
294                      "mpp12", "mpp13", "mpp14", "mpp15",
295                      "mpp16", "mpp17", "mpp18", "mpp19",
296                      "mpp20", "mpp21", "mpp22", "mpp23";
297                 marvell,function = "ge1";
298         };
299
300         sdio_pins: sdio-pins {
301                 marvell,pins = "mpp30", "mpp31", "mpp32",
302                                "mpp33", "mpp34", "mpp35";
303                 marvell,function = "sd0";
304         };
305
306         spi0_pins: spi0-pins {
307                 marvell,pins = "mpp36", "mpp37",
308                                "mpp38", "mpp39";
309                 marvell,function = "spi0";
310         };
311
312         uart2_pins: uart2-pins {
313                 marvell,pins = "mpp42", "mpp43";
314                 marvell,function = "uart2";
315         };
316
317         uart3_pins: uart3-pins {
318                 marvell,pins = "mpp44", "mpp45";
319                 marvell,function = "uart3";
320         };
321 };