2 * Copyright 2012 DENX Software Engineering GmbH
3 * Heiko Schocher <hs@denx.de>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 #include "skeleton.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
18 intc: interrupt-controller@fffee000 {
19 compatible = "ti,cp-intc";
21 #interrupt-cells = <1>;
23 reg = <0xfffee000 0x2000>;
27 compatible = "ti,da850-dsp";
28 reg = <0x11800000 0x40000>,
33 reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
34 interrupt-parent = <&intc>;
39 compatible = "simple-bus";
43 ranges = <0x0 0x01c00000 0x400000>;
44 interrupt-parent = <&intc>;
46 pmx_core: pinmux@14120 {
47 compatible = "pinctrl-single";
52 pinctrl-single,bit-per-mux;
53 pinctrl-single,register-width = <32>;
54 pinctrl-single,function-mask = <0xf>;
57 serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
58 pinctrl-single,bits = <
59 /* UART0_RTS UART0_CTS */
60 0x0c 0x22000000 0xff000000
63 serial0_rxtx_pins: pinmux_serial0_rxtx_pins {
64 pinctrl-single,bits = <
65 /* UART0_TXD UART0_RXD */
66 0x0c 0x00220000 0x00ff0000
69 serial1_rtscts_pins: pinmux_serial1_rtscts_pins {
70 pinctrl-single,bits = <
71 /* UART1_CTS UART1_RTS */
72 0x00 0x00440000 0x00ff0000
75 serial1_rxtx_pins: pinmux_serial1_rxtx_pins {
76 pinctrl-single,bits = <
77 /* UART1_TXD UART1_RXD */
78 0x10 0x22000000 0xff000000
81 serial2_rtscts_pins: pinmux_serial2_rtscts_pins {
82 pinctrl-single,bits = <
83 /* UART2_CTS UART2_RTS */
84 0x00 0x44000000 0xff000000
87 serial2_rxtx_pins: pinmux_serial2_rxtx_pins {
88 pinctrl-single,bits = <
89 /* UART2_TXD UART2_RXD */
90 0x10 0x00220000 0x00ff0000
93 i2c0_pins: pinmux_i2c0_pins {
94 pinctrl-single,bits = <
95 /* I2C0_SDA,I2C0_SCL */
96 0x10 0x00002200 0x0000ff00
99 i2c1_pins: pinmux_i2c1_pins {
100 pinctrl-single,bits = <
101 /* I2C1_SDA, I2C1_SCL */
102 0x10 0x00440000 0x00ff0000
105 mmc0_pins: pinmux_mmc_pins {
106 pinctrl-single,bits = <
107 /* MMCSD0_DAT[3] MMCSD0_DAT[2]
108 * MMCSD0_DAT[1] MMCSD0_DAT[0]
109 * MMCSD0_CMD MMCSD0_CLK
111 0x28 0x00222222 0x00ffffff
114 ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
115 pinctrl-single,bits = <
117 0xc 0x00000002 0x0000000f
120 ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
121 pinctrl-single,bits = <
123 0xc 0x00000020 0x000000f0
126 ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
127 pinctrl-single,bits = <
129 0x14 0x00000002 0x0000000f
132 ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
133 pinctrl-single,bits = <
135 0x14 0x00000020 0x000000f0
138 ecap0_pins: pinmux_ecap0_pins {
139 pinctrl-single,bits = <
141 0x8 0x20000000 0xf0000000
144 ecap1_pins: pinmux_ecap1_pins {
145 pinctrl-single,bits = <
147 0x4 0x40000000 0xf0000000
150 ecap2_pins: pinmux_ecap2_pins {
151 pinctrl-single,bits = <
153 0x4 0x00000004 0x0000000f
156 spi0_pins: pinmux_spi0_pins {
157 pinctrl-single,bits = <
158 /* SIMO, SOMI, CLK */
159 0xc 0x00001101 0x0000ff0f
162 spi0_cs0_pin: pinmux_spi0_cs0 {
163 pinctrl-single,bits = <
165 0x10 0x00000010 0x000000f0
168 spi0_cs3_pin: pinmux_spi0_cs3_pin {
169 pinctrl-single,bits = <
171 0xc 0x01000000 0x0f000000
174 spi1_pins: pinmux_spi1_pins {
175 pinctrl-single,bits = <
176 /* SIMO, SOMI, CLK */
177 0x14 0x00110100 0x00ff0f00
180 spi1_cs0_pin: pinmux_spi1_cs0 {
181 pinctrl-single,bits = <
183 0x14 0x00000010 0x000000f0
186 mdio_pins: pinmux_mdio_pins {
187 pinctrl-single,bits = <
188 /* MDIO_CLK, MDIO_D */
189 0x10 0x00000088 0x000000ff
192 mii_pins: pinmux_mii_pins {
193 pinctrl-single,bits = <
195 * MII_TXEN, MII_TXCLK, MII_COL
196 * MII_TXD_3, MII_TXD_2, MII_TXD_1
199 0x8 0x88888880 0xfffffff0
201 * MII_RXER, MII_CRS, MII_RXCLK
202 * MII_RXDV, MII_RXD_3, MII_RXD_2
203 * MII_RXD_1, MII_RXD_0
205 0xc 0x88888888 0xffffffff
208 lcd_pins: pinmux_lcd_pins {
209 pinctrl-single,bits = <
211 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
214 0x40 0x22222200 0xffffff00
216 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
217 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
219 0x44 0x22222222 0xffffffff
220 /* LCD_D[8], LCD_D[9] */
221 0x48 0x00000022 0x000000ff
224 0x48 0x02000000 0x0f000000
225 /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
226 0x4c 0x02000022 0x0f0000ff
229 vpif_capture_pins: vpif_capture_pins {
230 pinctrl-single,bits = <
231 /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */
232 0x38 0x11111111 0xffffffff
233 /* VP_DIN[10..15,0..1] */
234 0x3c 0x11111111 0xffffffff
236 0x40 0x00000011 0x000000ff
239 vpif_display_pins: vpif_display_pins {
240 pinctrl-single,bits = <
242 0x40 0x11111100 0xffffff00
243 /* VP_DOUT[10..15,0..1] */
244 0x44 0x11111111 0xffffffff
246 0x48 0x00000011 0x000000ff
248 * VP_CLKOUT3, VP_CLKIN3,
249 * VP_CLKOUT2, VP_CLKIN2
251 0x4c 0x00111100 0x00ffff00
255 prictrl: priority-controller@14110 {
256 compatible = "ti,da850-mstpri";
257 reg = <0x14110 0x0c>;
260 cfgchip: chip-controller@1417c {
261 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
262 reg = <0x1417c 0x14>;
265 compatible = "ti,da830-usb-phy";
271 compatible = "ti,edma3-tpcc";
272 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
274 reg-names = "edma3_cc";
275 interrupts = <11 12>;
276 interrupt-names = "edma3_ccint", "edma3_ccerrint";
279 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
281 edma0_tptc0: tptc@8000 {
282 compatible = "ti,edma3-tptc";
283 reg = <0x8000 0x400>;
285 interrupt-names = "edm3_tcerrint";
287 edma0_tptc1: tptc@8400 {
288 compatible = "ti,edma3-tptc";
289 reg = <0x8400 0x400>;
291 interrupt-names = "edm3_tcerrint";
294 compatible = "ti,edma3-tpcc";
295 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
296 reg = <0x230000 0x8000>;
297 reg-names = "edma3_cc";
298 interrupts = <93 94>;
299 interrupt-names = "edma3_ccint", "edma3_ccerrint";
302 ti,tptcs = <&edma1_tptc0 7>;
304 edma1_tptc0: tptc@238000 {
305 compatible = "ti,edma3-tptc";
306 reg = <0x238000 0x400>;
308 interrupt-names = "edm3_tcerrint";
310 serial0: serial@42000 {
311 compatible = "ti,da830-uart", "ns16550a";
312 reg = <0x42000 0x100>;
318 serial1: serial@10c000 {
319 compatible = "ti,da830-uart", "ns16550a";
320 reg = <0x10c000 0x100>;
326 serial2: serial@10d000 {
327 compatible = "ti,da830-uart", "ns16550a";
328 reg = <0x10d000 0x100>;
335 compatible = "ti,da830-rtc";
336 reg = <0x23000 0x1000>;
342 compatible = "ti,davinci-i2c";
343 reg = <0x22000 0x1000>;
345 #address-cells = <1>;
350 compatible = "ti,davinci-i2c";
351 reg = <0x228000 0x1000>;
353 #address-cells = <1>;
358 compatible = "ti,davinci-wdt";
359 reg = <0x21000 0x1000>;
363 compatible = "ti,da830-mmc";
364 reg = <0x40000 0x1000>;
368 dmas = <&edma0 16 0>, <&edma0 17 0>;
369 dma-names = "rx", "tx";
373 compatible = "ti,da850-vpif";
374 reg = <0x217000 0x1000>;
378 /* VPIF capture port */
380 #address-cells = <1>;
384 /* VPIF display port */
386 #address-cells = <1>;
391 compatible = "ti,da830-mmc";
392 reg = <0x21b000 0x1000>;
396 dmas = <&edma1 28 0>, <&edma1 29 0>;
397 dma-names = "rx", "tx";
400 ehrpwm0: pwm@300000 {
401 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
404 reg = <0x300000 0x2000>;
407 ehrpwm1: pwm@302000 {
408 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
411 reg = <0x302000 0x2000>;
415 compatible = "ti,da850-ecap", "ti,am3352-ecap",
418 reg = <0x306000 0x80>;
422 compatible = "ti,da850-ecap", "ti,am3352-ecap",
425 reg = <0x307000 0x80>;
429 compatible = "ti,da850-ecap", "ti,am3352-ecap",
432 reg = <0x308000 0x80>;
436 #address-cells = <1>;
438 compatible = "ti,da830-spi";
439 reg = <0x41000 0x1000>;
441 ti,davinci-spi-intr-line = <1>;
443 dmas = <&edma0 14 0>, <&edma0 15 0>;
444 dma-names = "rx", "tx";
448 #address-cells = <1>;
450 compatible = "ti,da830-spi";
451 reg = <0x30e000 0x1000>;
453 ti,davinci-spi-intr-line = <1>;
455 dmas = <&edma0 18 0>, <&edma0 19 0>;
456 dma-names = "rx", "tx";
460 compatible = "ti,da830-musb";
461 reg = <0x200000 0x1000>;
464 interrupt-names = "mc";
467 phy-names = "usb-phy";
470 #address-cells = <1>;
473 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
474 &cppi41dma 2 0 &cppi41dma 3 0
475 &cppi41dma 0 1 &cppi41dma 1 1
476 &cppi41dma 2 1 &cppi41dma 3 1>;
478 "rx1", "rx2", "rx3", "rx4",
479 "tx1", "tx2", "tx3", "tx4";
481 cppi41dma: dma-controller@201000 {
482 compatible = "ti,da830-cppi41";
483 reg = <0x201000 0x1000
486 reg-names = "controller",
487 "scheduler", "queuemgr";
495 compatible = "ti,da850-ahci";
496 reg = <0x218000 0x2000>, <0x22c018 0x4>;
501 compatible = "ti,davinci_mdio";
502 #address-cells = <1>;
504 reg = <0x224000 0x1000>;
507 eth0: ethernet@220000 {
508 compatible = "ti,davinci-dm6467-emac";
509 reg = <0x220000 0x4000>;
510 ti,davinci-ctrl-reg-offset = <0x3000>;
511 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
512 ti,davinci-ctrl-ram-offset = <0>;
513 ti,davinci-ctrl-ram-size = <0x2000>;
514 local-mac-address = [ 00 00 00 00 00 00 ];
523 compatible = "ti,da830-ohci";
524 reg = <0x225000 0x1000>;
527 phy-names = "usb-phy";
531 compatible = "ti,dm6441-gpio";
534 reg = <0x226000 0x1000>;
535 interrupts = <42 IRQ_TYPE_EDGE_BOTH
536 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
537 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
538 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
539 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
541 ti,davinci-gpio-unbanked = <0>;
543 interrupt-controller;
544 #interrupt-cells = <2>;
546 pinconf: pin-controller@22c00c {
547 compatible = "ti,da850-pupd";
548 reg = <0x22c00c 0x8>;
552 mcasp0: mcasp@100000 {
553 compatible = "ti,da830-mcasp-audio";
554 reg = <0x100000 0x2000>,
556 reg-names = "mpu", "dat";
558 interrupt-names = "common";
562 dma-names = "tx", "rx";
565 lcdc: display@213000 {
566 compatible = "ti,da850-tilcdc";
567 reg = <0x213000 0x1000>;
569 max-pixelclock = <37500>;
573 aemif: aemif@68000000 {
574 compatible = "ti,da850-aemif";
575 #address-cells = <2>;
578 reg = <0x68000000 0x00008000>;
579 ranges = <0 0 0x60000000 0x08000000
580 1 0 0x68000000 0x00008000>;
583 memctrl: memory-controller@b0000000 {
584 compatible = "ti,da850-ddr-controller";
585 reg = <0xb0000000 0xe8>;