git.sur5r.net Git - u-boot/blob - arch/arm/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "TI DRA742";
  15         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  16
  17         chosen {
  18                 stdout-path = &uart1;
  19                 tick-timer = &timer2;
  20         };
  21
  22         memory {
  23                 device_type = "memory";
  24                 reg = <0x80000000 0x60000000>; /* 1536 MB */
  25         };
  26
  27         evm_3v3_sd: fixedregulator-sd {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "evm_3v3_sd";
  30                 regulator-min-microvolt = <3300000>;
  31                 regulator-max-microvolt = <3300000>;
  32                 enable-active-high;
  33                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  34         };
  35
  36         mmc2_3v3: fixedregulator-mmc2 {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "mmc2_3v3";
  39                 regulator-min-microvolt = <3300000>;
  40                 regulator-max-microvolt = <3300000>;
  41         };
  42
  43         extcon_usb1: extcon_usb1 {
  44                 compatible = "linux,extcon-usb-gpio";
  45                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  46         };
  47
  48         extcon_usb2: extcon_usb2 {
  49                 compatible = "linux,extcon-usb-gpio";
  50                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  51         };
  52
  53         vtt_fixed: fixedregulator-vtt {
  54                 compatible = "regulator-fixed";
  55                 regulator-name = "vtt_fixed";
  56                 regulator-min-microvolt = <1350000>;
  57                 regulator-max-microvolt = <1350000>;
  58                 regulator-always-on;
  59                 regulator-boot-on;
  60                 enable-active-high;
  61                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
  62         };
  63 };
  64
  65 &dra7_pmx_core {
  66         pinctrl-names = "default";
  67         pinctrl-0 = <&vtt_pin>;
  68
  69         vtt_pin: pinmux_vtt_pin {
  70                 pinctrl-single,pins = <
  71                         0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
  72                 >;
  73         };
  74
  75         i2c1_pins: pinmux_i2c1_pins {
  76                 pinctrl-single,pins = <
  77                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
  78                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
  79                 >;
  80         };
  81
  82         i2c2_pins: pinmux_i2c2_pins {
  83                 pinctrl-single,pins = <
  84                         0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
  85                         0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
  86                 >;
  87         };
  88
  89         i2c3_pins: pinmux_i2c3_pins {
  90                 pinctrl-single,pins = <
  91                         0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
  92                         0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
  93                 >;
  94         };
  95
  96         mcspi1_pins: pinmux_mcspi1_pins {
  97                 pinctrl-single,pins = <
  98                         0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
  99                         0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
 100                         0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
 101                         0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
 102                         0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
 103                         0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
 104                 >;
 105         };
 106
 107         mcspi2_pins: pinmux_mcspi2_pins {
 108                 pinctrl-single,pins = <
 109                         0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
 110                         0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 111                         0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 112                         0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
 113                 >;
 114         };
 115
 116         uart1_pins: pinmux_uart1_pins {
 117                 pinctrl-single,pins = <
 118                         0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
 119                         0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
 120                         0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
 121                         0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
 122                 >;
 123         };
 124
 125         uart2_pins: pinmux_uart2_pins {
 126                 pinctrl-single,pins = <
 127                         0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
 128                         0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
 129                         0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
 130                         0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
 131                 >;
 132         };
 133
 134         uart3_pins: pinmux_uart3_pins {
 135                 pinctrl-single,pins = <
 136                         0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
 137                         0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 138                 >;
 139         };
 140
 141         qspi1_pins: pinmux_qspi1_pins {
 142                 pinctrl-single,pins = <
 143                         0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
 144                         0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
 145                         0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
 146                         0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
 147                         0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
 148                         0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
 149                         0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
 150                         0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
 151                         0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
 152                         0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
 153                 >;
 154         };
 155
 156         usb1_pins: pinmux_usb1_pins {
 157                 pinctrl-single,pins = <
 158                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 159                 >;
 160         };
 161
 162         usb2_pins: pinmux_usb2_pins {
 163                 pinctrl-single,pins = <
 164                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 165                 >;
 166         };
 167
 168         nand_flash_x16: nand_flash_x16 {
 169                 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
 170                  * So NAND flash requires following switch settings:
 171                  * SW5.9 (GPMC_WPN) = LOW
 172                  * SW5.1 (NAND_BOOTn) = HIGH */
 173                 pinctrl-single,pins = <
 174                         0x0     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad0     */
 175                         0x4     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad1     */
 176                         0x8     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad2     */
 177                         0xc     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad3     */
 178                         0x10    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad4     */
 179                         0x14    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad5     */
 180                         0x18    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad6     */
 181                         0x1c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad7     */
 182                         0x20    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad8     */
 183                         0x24    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad9     */
 184                         0x28    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad10    */
 185                         0x2c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad11    */
 186                         0x30    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad12    */
 187                         0x34    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad13    */
 188                         0x38    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad14    */
 189                         0x3c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad15    */
 190                         0xd8    (PIN_INPUT_PULLUP  | MUX_MODE0) /* gpmc_wait0   */
 191                         0xcc    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_wen     */
 192                         0xb4    (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0    */
 193                         0xc4    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_advn_ale */
 194                         0xc8    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_oen_ren  */
 195                         0xd0    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_be0n_cle */
 196                 >;
 197         };
 198
 199         cpsw_default: cpsw_default {
 200                 pinctrl-single,pins = <
 201                         /* Slave 1 */
 202                         0x250 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txc.rgmii0_txc */
 203                         0x254 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txctl.rgmii0_txctl */
 204                         0x258 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_td3.rgmii0_txd3 */
 205                         0x25c (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd2.rgmii0_txd2 */
 206                         0x260 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd1.rgmii0_txd1 */
 207                         0x264 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd0.rgmii0_txd0 */
 208                         0x268 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxc.rgmii0_rxc */
 209                         0x26c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxctl.rgmii0_rxctl */
 210                         0x270 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd3.rgmii0_rxd3 */
 211                         0x274 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd2.rgmii0_rxd2 */
 212                         0x278 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd1.rgmii0_rxd1 */
 213                         0x27c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd0.rgmii0_rxd0 */
 214
 215                         /* Slave 2 */
 216                         0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
 217                         0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
 218                         0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
 219                         0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
 220                         0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
 221                         0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
 222                         0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
 223                         0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
 224                         0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
 225                         0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
 226                         0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
 227                         0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
 228                 >;
 229
 230         };
 231
 232         cpsw_sleep: cpsw_sleep {
 233                 pinctrl-single,pins = <
 234                         /* Slave 1 */
 235                         0x250 (MUX_MODE15)
 236                         0x254 (MUX_MODE15)
 237                         0x258 (MUX_MODE15)
 238                         0x25c (MUX_MODE15)
 239                         0x260 (MUX_MODE15)
 240                         0x264 (MUX_MODE15)
 241                         0x268 (MUX_MODE15)
 242                         0x26c (MUX_MODE15)
 243                         0x270 (MUX_MODE15)
 244                         0x274 (MUX_MODE15)
 245                         0x278 (MUX_MODE15)
 246                         0x27c (MUX_MODE15)
 247
 248                         /* Slave 2 */
 249                         0x198 (MUX_MODE15)
 250                         0x19c (MUX_MODE15)
 251                         0x1a0 (MUX_MODE15)
 252                         0x1a4 (MUX_MODE15)
 253                         0x1a8 (MUX_MODE15)
 254                         0x1ac (MUX_MODE15)
 255                         0x1b0 (MUX_MODE15)
 256                         0x1b4 (MUX_MODE15)
 257                         0x1b8 (MUX_MODE15)
 258                         0x1bc (MUX_MODE15)
 259                         0x1c0 (MUX_MODE15)
 260                         0x1c4 (MUX_MODE15)
 261                 >;
 262         };
 263
 264         davinci_mdio_default: davinci_mdio_default {
 265                 pinctrl-single,pins = <
 266                         0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
 267                         0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
 268                 >;
 269         };
 270
 271         davinci_mdio_sleep: davinci_mdio_sleep {
 272                 pinctrl-single,pins = <
 273                         0x23c (MUX_MODE15)
 274                         0x240 (MUX_MODE15)
 275                 >;
 276         };
 277
 278         dcan1_pins_default: dcan1_pins_default {
 279                 pinctrl-single,pins = <
 280                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 281                         0x418   (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
 282                 >;
 283         };
 284
 285         dcan1_pins_sleep: dcan1_pins_sleep {
 286                 pinctrl-single,pins = <
 287                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 288                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 289                 >;
 290         };
 291 };
 292
 293 &i2c1 {
 294         status = "okay";
 295         pinctrl-names = "default";
 296         pinctrl-0 = <&i2c1_pins>;
 297         clock-frequency = <400000>;
 298
 299         tps659038: tps659038@58 {
 300                 compatible = "ti,tps659038";
 301                 reg = <0x58>;
 302
 303                 tps659038_pmic {
 304                         compatible = "ti,tps659038-pmic";
 305
 306                         regulators {
 307                                 smps123_reg: smps123 {
 308                                         /* VDD_MPU */
 309                                         regulator-name = "smps123";
 310                                         regulator-min-microvolt = < 850000>;
 311                                         regulator-max-microvolt = <1250000>;
 312                                         regulator-always-on;
 313                                         regulator-boot-on;
 314                                 };
 315
 316                                 smps45_reg: smps45 {
 317                                         /* VDD_DSPEVE */
 318                                         regulator-name = "smps45";
 319                                         regulator-min-microvolt = < 850000>;
 320                                         regulator-max-microvolt = <1150000>;
 321                                         regulator-always-on;
 322                                         regulator-boot-on;
 323                                 };
 324
 325                                 smps6_reg: smps6 {
 326                                         /* VDD_GPU - over VDD_SMPS6 */
 327                                         regulator-name = "smps6";
 328                                         regulator-min-microvolt = <850000>;
 329                                         regulator-max-microvolt = <1250000>;
 330                                         regulator-always-on;
 331                                         regulator-boot-on;
 332                                 };
 333
 334                                 smps7_reg: smps7 {
 335                                         /* CORE_VDD */
 336                                         regulator-name = "smps7";
 337                                         regulator-min-microvolt = <850000>;
 338                                         regulator-max-microvolt = <1060000>;
 339                                         regulator-always-on;
 340                                         regulator-boot-on;
 341                                 };
 342
 343                                 smps8_reg: smps8 {
 344                                         /* VDD_IVAHD */
 345                                         regulator-name = "smps8";
 346                                         regulator-min-microvolt = < 850000>;
 347                                         regulator-max-microvolt = <1250000>;
 348                                         regulator-always-on;
 349                                         regulator-boot-on;
 350                                 };
 351
 352                                 smps9_reg: smps9 {
 353                                         /* VDDS1V8 */
 354                                         regulator-name = "smps9";
 355                                         regulator-min-microvolt = <1800000>;
 356                                         regulator-max-microvolt = <1800000>;
 357                                         regulator-always-on;
 358                                         regulator-boot-on;
 359                                 };
 360
 361                                 ldo1_reg: ldo1 {
 362                                         /* LDO1_OUT --> SDIO  */
 363                                         regulator-name = "ldo1";
 364                                         regulator-min-microvolt = <1800000>;
 365                                         regulator-max-microvolt = <3300000>;
 366                                         regulator-boot-on;
 367                                 };
 368
 369                                 ldo2_reg: ldo2 {
 370                                         /* VDD_RTCIO */
 371                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 372                                         regulator-name = "ldo2";
 373                                         regulator-min-microvolt = <3300000>;
 374                                         regulator-max-microvolt = <3300000>;
 375                                         regulator-always-on;
 376                                         regulator-boot-on;
 377                                 };
 378
 379                                 ldo3_reg: ldo3 {
 380                                         /* VDDA_1V8_PHY */
 381                                         regulator-name = "ldo3";
 382                                         regulator-min-microvolt = <1800000>;
 383                                         regulator-max-microvolt = <1800000>;
 384                                         regulator-always-on;
 385                                         regulator-boot-on;
 386                                 };
 387
 388                                 ldo9_reg: ldo9 {
 389                                         /* VDD_RTC */
 390                                         regulator-name = "ldo9";
 391                                         regulator-min-microvolt = <1050000>;
 392                                         regulator-max-microvolt = <1050000>;
 393                                         regulator-always-on;
 394                                         regulator-boot-on;
 395                                 };
 396
 397                                 ldoln_reg: ldoln {
 398                                         /* VDDA_1V8_PLL */
 399                                         regulator-name = "ldoln";
 400                                         regulator-min-microvolt = <1800000>;
 401                                         regulator-max-microvolt = <1800000>;
 402                                         regulator-always-on;
 403                                         regulator-boot-on;
 404                                 };
 405
 406                                 ldousb_reg: ldousb {
 407                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 408                                         regulator-name = "ldousb";
 409                                         regulator-min-microvolt = <3300000>;
 410                                         regulator-max-microvolt = <3300000>;
 411                                         regulator-boot-on;
 412                                 };
 413                         };
 414                 };
 415         };
 416
 417         pcf_gpio_21: gpio@21 {
 418                 compatible = "ti,pcf8575";
 419                 reg = <0x21>;
 420                 lines-initial-states = <0x1408>;
 421                 gpio-controller;
 422                 #gpio-cells = <2>;
 423                 interrupt-parent = <&gpio6>;
 424                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 425                 interrupt-controller;
 426                 #interrupt-cells = <2>;
 427                 u-boot,i2c-offset-len = <0>;
 428         };
 429
 430 };
 431
 432 &i2c2 {
 433         status = "okay";
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&i2c2_pins>;
 436         clock-frequency = <400000>;
 437 };
 438
 439 &i2c3 {
 440         status = "okay";
 441         pinctrl-names = "default";
 442         pinctrl-0 = <&i2c3_pins>;
 443         clock-frequency = <400000>;
 444 };
 445
 446 &mcspi1 {
 447         status = "okay";
 448         pinctrl-names = "default";
 449         pinctrl-0 = <&mcspi1_pins>;
 450 };
 451
 452 &mcspi2 {
 453         status = "okay";
 454         pinctrl-names = "default";
 455         pinctrl-0 = <&mcspi2_pins>;
 456 };
 457
 458 &uart1 {
 459         status = "okay";
 460         pinctrl-names = "default";
 461         pinctrl-0 = <&uart1_pins>;
 462         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 463                               <&dra7_pmx_core 0x3e0>;
 464 };
 465
 466 &uart2 {
 467         status = "okay";
 468         pinctrl-names = "default";
 469         pinctrl-0 = <&uart2_pins>;
 470 };
 471
 472 &uart3 {
 473         status = "okay";
 474         pinctrl-names = "default";
 475         pinctrl-0 = <&uart3_pins>;
 476 };
 477
 478 &mmc1 {
 479         status = "okay";
 480         vmmc-supply = <&evm_3v3_sd>;
 481         vmmc_aux-supply = <&ldo1_reg>;
 482         bus-width = <4>;
 483         /*
 484          * SDCD signal is not being used here - using the fact that GPIO mode
 485          * is always hardwired.
 486          */
 487         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 488 };
 489
 490 &mmc2 {
 491         status = "okay";
 492         vmmc-supply = <&mmc2_3v3>;
 493         bus-width = <8>;
 494 };
 495
 496 &cpu0 {
 497         cpu0-supply = <&smps123_reg>;
 498 };
 499
 500 &qspi {
 501         status = "okay";
 502         pinctrl-names = "default";
 503         pinctrl-0 = <&qspi1_pins>;
 504
 505         spi-max-frequency = <76800000>;
 506         m25p80@0 {
 507                 compatible = "s25fl256s1","spi-flash";
 508                 spi-max-frequency = <76800000>;
 509                 reg = <0>;
 510                 spi-tx-bus-width = <1>;
 511                 spi-rx-bus-width = <4>;
 512                 #address-cells = <1>;
 513                 #size-cells = <1>;
 514
 515                 /* MTD partition table.
 516                  * The ROM checks the first four physical blocks
 517                  * for a valid file to boot and the flash here is
 518                  * 64KiB block size.
 519                  */
 520                 partition@0 {
 521                         label = "QSPI.SPL";
 522                         reg = <0x00000000 0x000010000>;
 523                 };
 524                 partition@1 {
 525                         label = "QSPI.SPL.backup1";
 526                         reg = <0x00010000 0x00010000>;
 527                 };
 528                 partition@2 {
 529                         label = "QSPI.SPL.backup2";
 530                         reg = <0x00020000 0x00010000>;
 531                 };
 532                 partition@3 {
 533                         label = "QSPI.SPL.backup3";
 534                         reg = <0x00030000 0x00010000>;
 535                 };
 536                 partition@4 {
 537                         label = "QSPI.u-boot";
 538                         reg = <0x00040000 0x00100000>;
 539                 };
 540                 partition@5 {
 541                         label = "QSPI.u-boot-spl-os";
 542                         reg = <0x00140000 0x00080000>;
 543                 };
 544                 partition@6 {
 545                         label = "QSPI.u-boot-env";
 546                         reg = <0x001c0000 0x00010000>;
 547                 };
 548                 partition@7 {
 549                         label = "QSPI.u-boot-env.backup1";
 550                         reg = <0x001d0000 0x0010000>;
 551                 };
 552                 partition@8 {
 553                         label = "QSPI.kernel";
 554                         reg = <0x001e0000 0x0800000>;
 555                 };
 556                 partition@9 {
 557                         label = "QSPI.file-system";
 558                         reg = <0x009e0000 0x01620000>;
 559                 };
 560         };
 561 };
 562
 563 &omap_dwc3_1 {
 564         extcon = <&extcon_usb1>;
 565 };
 566
 567 &omap_dwc3_2 {
 568         extcon = <&extcon_usb2>;
 569 };
 570
 571 &usb1 {
 572         dr_mode = "peripheral";
 573         pinctrl-names = "default";
 574         pinctrl-0 = <&usb1_pins>;
 575 };
 576
 577 &usb2 {
 578         dr_mode = "host";
 579         pinctrl-names = "default";
 580         pinctrl-0 = <&usb2_pins>;
 581 };
 582
 583 &elm {
 584         status = "okay";
 585 };
 586
 587 &gpmc {
 588         status = "okay";
 589         pinctrl-names = "default";
 590         pinctrl-0 = <&nand_flash_x16>;
 591         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 592         nand@0,0 {
 593                 reg = <0 0 4>;          /* device IO registers */
 594                 ti,nand-ecc-opt = "bch8";
 595                 ti,elm-id = <&elm>;
 596                 nand-bus-width = <16>;
 597                 gpmc,device-width = <2>;
 598                 gpmc,sync-clk-ps = <0>;
 599                 gpmc,cs-on-ns = <0>;
 600                 gpmc,cs-rd-off-ns = <80>;
 601                 gpmc,cs-wr-off-ns = <80>;
 602                 gpmc,adv-on-ns = <0>;
 603                 gpmc,adv-rd-off-ns = <60>;
 604                 gpmc,adv-wr-off-ns = <60>;
 605                 gpmc,we-on-ns = <10>;
 606                 gpmc,we-off-ns = <50>;
 607                 gpmc,oe-on-ns = <4>;
 608                 gpmc,oe-off-ns = <40>;
 609                 gpmc,access-ns = <40>;
 610                 gpmc,wr-access-ns = <80>;
 611                 gpmc,rd-cycle-ns = <80>;
 612                 gpmc,wr-cycle-ns = <80>;
 613                 gpmc,bus-turnaround-ns = <0>;
 614                 gpmc,cycle2cycle-delay-ns = <0>;
 615                 gpmc,clk-activation-ns = <0>;
 616                 gpmc,wait-monitoring-ns = <0>;
 617                 gpmc,wr-data-mux-bus-ns = <0>;
 618                 /* MTD partition table */
 619                 /* All SPL-* partitions are sized to minimal length
 620                  * which can be independently programmable. For
 621                  * NAND flash this is equal to size of erase-block */
 622                 #address-cells = <1>;
 623                 #size-cells = <1>;
 624                 partition@0 {
 625                         label = "NAND.SPL";
 626                         reg = <0x00000000 0x000020000>;
 627                 };
 628                 partition@1 {
 629                         label = "NAND.SPL.backup1";
 630                         reg = <0x00020000 0x00020000>;
 631                 };
 632                 partition@2 {
 633                         label = "NAND.SPL.backup2";
 634                         reg = <0x00040000 0x00020000>;
 635                 };
 636                 partition@3 {
 637                         label = "NAND.SPL.backup3";
 638                         reg = <0x00060000 0x00020000>;
 639                 };
 640                 partition@4 {
 641                         label = "NAND.u-boot-spl-os";
 642                         reg = <0x00080000 0x00040000>;
 643                 };
 644                 partition@5 {
 645                         label = "NAND.u-boot";
 646                         reg = <0x000c0000 0x00100000>;
 647                 };
 648                 partition@6 {
 649                         label = "NAND.u-boot-env";
 650                         reg = <0x001c0000 0x00020000>;
 651                 };
 652                 partition@7 {
 653                         label = "NAND.u-boot-env.backup1";
 654                         reg = <0x001e0000 0x00020000>;
 655                 };
 656                 partition@8 {
 657                         label = "NAND.kernel";
 658                         reg = <0x00200000 0x00800000>;
 659                 };
 660                 partition@9 {
 661                         label = "NAND.file-system";
 662                         reg = <0x00a00000 0x0f600000>;
 663                 };
 664         };
 665 };
 666
 667 &usb2_phy1 {
 668         phy-supply = <&ldousb_reg>;
 669 };
 670
 671 &usb2_phy2 {
 672         phy-supply = <&ldousb_reg>;
 673 };
 674
 675 &gpio7 {
 676         ti,no-reset-on-init;
 677         ti,no-idle-on-init;
 678 };
 679
 680 &mac {
 681         status = "okay";
 682         pinctrl-names = "default", "sleep";
 683         pinctrl-0 = <&cpsw_default>;
 684         pinctrl-1 = <&cpsw_sleep>;
 685         dual_emac;
 686 };
 687
 688 &cpsw_emac0 {
 689         phy_id = <&davinci_mdio>, <2>;
 690         phy-mode = "rgmii";
 691         dual_emac_res_vlan = <1>;
 692 };
 693
 694 &cpsw_emac1 {
 695         phy_id = <&davinci_mdio>, <3>;
 696         phy-mode = "rgmii";
 697         dual_emac_res_vlan = <2>;
 698 };
 699
 700 &davinci_mdio {
 701         pinctrl-names = "default", "sleep";
 702         pinctrl-0 = <&davinci_mdio_default>;
 703         pinctrl-1 = <&davinci_mdio_sleep>;
 704 };
 705
 706 &dcan1 {
 707         status = "ok";
 708         pinctrl-names = "default", "sleep", "active";
 709         pinctrl-0 = <&dcan1_pins_sleep>;
 710         pinctrl-1 = <&dcan1_pins_sleep>;
 711         pinctrl-2 = <&dcan1_pins_default>;
 712 };