git.sur5r.net Git - u-boot/blob - arch/arm/dts/dra72-evm-common.dtsi

   1 /*
   2  * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra72x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  15
  16         chosen {
  17                 stdout-path = &uart1;
  18                 tick-timer = &timer2;
  19         };
  20
  21         aliases {
  22                 display0 = &hdmi0;
  23         };
  24
  25         evm_3v3: fixedregulator-evm_3v3 {
  26                 compatible = "regulator-fixed";
  27                 regulator-name = "evm_3v3";
  28                 regulator-min-microvolt = <3300000>;
  29                 regulator-max-microvolt = <3300000>;
  30         };
  31
  32         extcon_usb1: extcon_usb1 {
  33                 compatible = "linux,extcon-usb-gpio";
  34                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  35         };
  36
  37         extcon_usb2: extcon_usb2 {
  38                 compatible = "linux,extcon-usb-gpio";
  39                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  40         };
  41
  42         hdmi0: connector {
  43                 compatible = "hdmi-connector";
  44                 label = "hdmi";
  45
  46                 type = "a";
  47
  48                 port {
  49                         hdmi_connector_in: endpoint {
  50                                 remote-endpoint = <&tpd12s015_out>;
  51                         };
  52                 };
  53         };
  54
  55         tpd12s015: encoder {
  56                 compatible = "ti,tpd12s015";
  57
  58                 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
  59                         <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
  60                         <&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
  61
  62                 ports {
  63                         #address-cells = <1>;
  64                         #size-cells = <0>;
  65
  66                         port@0 {
  67                                 reg = <0>;
  68
  69                                 tpd12s015_in: endpoint {
  70                                         remote-endpoint = <&hdmi_out>;
  71                                 };
  72                         };
  73
  74                         port@1 {
  75                                 reg = <1>;
  76
  77                                 tpd12s015_out: endpoint {
  78                                         remote-endpoint = <&hdmi_connector_in>;
  79                                 };
  80                         };
  81                 };
  82         };
  83 };
  84
  85 &dra7_pmx_core {
  86         mmc1_pins_default: mmc1_pins_default {
  87                 pinctrl-single,pins = <
  88                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  89                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  90                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  91                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  92                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  93                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  94                 >;
  95         };
  96
  97         mmc2_pins_default: mmc2_pins_default {
  98                 pinctrl-single,pins = <
  99                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 100                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 101                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 102                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 103                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 104                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 105                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 106                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 107                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 108                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 109                 >;
 110         };
 111
 112         dcan1_pins_default: dcan1_pins_default {
 113                 pinctrl-single,pins = <
 114                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 115                         0x418   (PULL_UP | MUX_MODE1)   /* wakeup0.dcan1_rx */
 116                 >;
 117         };
 118
 119         dcan1_pins_sleep: dcan1_pins_sleep {
 120                 pinctrl-single,pins = <
 121                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 122                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 123                 >;
 124         };
 125 };
 126
 127 &i2c1 {
 128         status = "okay";
 129         clock-frequency = <400000>;
 130
 131         tps65917: tps65917@58 {
 132                 compatible = "ti,tps65917";
 133                 reg = <0x58>;
 134
 135                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
 136                 interrupt-controller;
 137                 #interrupt-cells = <2>;
 138
 139                 ti,system-power-controller;
 140
 141                 tps65917_pmic {
 142                         compatible = "ti,tps65917-pmic";
 143
 144                         tps65917_regulators: regulators {
 145                                 smps1_reg: smps1 {
 146                                         /* VDD_MPU */
 147                                         regulator-name = "smps1";
 148                                         regulator-min-microvolt = <850000>;
 149                                         regulator-max-microvolt = <1250000>;
 150                                         regulator-always-on;
 151                                         regulator-boot-on;
 152                                 };
 153
 154                                 smps2_reg: smps2 {
 155                                         /* VDD_CORE */
 156                                         regulator-name = "smps2";
 157                                         regulator-min-microvolt = <850000>;
 158                                         regulator-max-microvolt = <1060000>;
 159                                         regulator-boot-on;
 160                                         regulator-always-on;
 161                                 };
 162
 163                                 smps3_reg: smps3 {
 164                                         /* VDD_GPU IVA DSPEVE */
 165                                         regulator-name = "smps3";
 166                                         regulator-min-microvolt = <850000>;
 167                                         regulator-max-microvolt = <1250000>;
 168                                         regulator-boot-on;
 169                                         regulator-always-on;
 170                                 };
 171
 172                                 smps4_reg: smps4 {
 173                                         /* VDDS1V8 */
 174                                         regulator-name = "smps4";
 175                                         regulator-min-microvolt = <1800000>;
 176                                         regulator-max-microvolt = <1800000>;
 177                                         regulator-always-on;
 178                                         regulator-boot-on;
 179                                 };
 180
 181                                 smps5_reg: smps5 {
 182                                         /* VDD_DDR */
 183                                         regulator-name = "smps5";
 184                                         regulator-min-microvolt = <1350000>;
 185                                         regulator-max-microvolt = <1350000>;
 186                                         regulator-boot-on;
 187                                         regulator-always-on;
 188                                 };
 189
 190                                 ldo1_reg: ldo1 {
 191                                         /* LDO1_OUT --> SDIO  */
 192                                         regulator-name = "ldo1";
 193                                         regulator-min-microvolt = <1800000>;
 194                                         regulator-max-microvolt = <3300000>;
 195                                         regulator-always-on;
 196                                         regulator-boot-on;
 197                                         regulator-allow-bypass;
 198                                 };
 199
 200                                 ldo3_reg: ldo3 {
 201                                         /* VDDA_1V8_PHY */
 202                                         regulator-name = "ldo3";
 203                                         regulator-min-microvolt = <1800000>;
 204                                         regulator-max-microvolt = <1800000>;
 205                                         regulator-boot-on;
 206                                         regulator-always-on;
 207                                 };
 208
 209                                 ldo5_reg: ldo5 {
 210                                         /* VDDA_1V8_PLL */
 211                                         regulator-name = "ldo5";
 212                                         regulator-min-microvolt = <1800000>;
 213                                         regulator-max-microvolt = <1800000>;
 214                                         regulator-always-on;
 215                                         regulator-boot-on;
 216                                 };
 217
 218                                 ldo4_reg: ldo4 {
 219                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 220                                         regulator-name = "ldo4";
 221                                         regulator-min-microvolt = <3300000>;
 222                                         regulator-max-microvolt = <3300000>;
 223                                         regulator-boot-on;
 224                                 };
 225                         };
 226                 };
 227
 228                 tps65917_power_button {
 229                         compatible = "ti,palmas-pwrbutton";
 230                         interrupt-parent = <&tps65917>;
 231                         interrupts = <1 IRQ_TYPE_NONE>;
 232                         wakeup-source;
 233                         ti,palmas-long-press-seconds = <6>;
 234                 };
 235         };
 236
 237         pcf_gpio_21: gpio@21 {
 238                 compatible = "ti,pcf8575";
 239                 u-boot,i2c-offset-len = <0>;
 240                 reg = <0x21>;
 241                 lines-initial-states = <0x1408>;
 242                 gpio-controller;
 243                 #gpio-cells = <2>;
 244
 245                 interrupt-controller;
 246                 #interrupt-cells = <2>;
 247         };
 248 };
 249
 250 &i2c5 {
 251         status = "okay";
 252         clock-frequency = <400000>;
 253
 254         pcf_hdmi: pcf8575@26 {
 255                 compatible = "nxp,pcf8575";
 256                 u-boot,i2c-offset-len = <0>;
 257                 reg = <0x26>;
 258                 gpio-controller;
 259                 #gpio-cells = <2>;
 260                 /*
 261                  * initial state is used here to keep the mdio interface
 262                  * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
 263                  * VIN2_S0 driven high otherwise Ethernet stops working
 264                  * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
 265                  */
 266                 lines-initial-states = <0x0f2b>;
 267
 268                 p1 {
 269                         /* vin6_sel_s0: high: VIN6, low: audio */
 270                         gpio-hog;
 271                         gpios = <1 GPIO_ACTIVE_HIGH>;
 272                         output-low;
 273                         line-name = "vin6_sel_s0";
 274                 };
 275         };
 276 };
 277
 278 &uart1 {
 279         status = "okay";
 280         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 281                               <&dra7_pmx_core 0x3e0>;
 282 };
 283
 284 &elm {
 285         status = "okay";
 286 };
 287
 288 &gpmc {
 289         /*
 290          * For the existing IOdelay configuration via U-Boot we don't
 291          * support NAND on dra72-evm. Keep it disabled. Enabling it
 292          * requires a different configuration by U-Boot.
 293          */
 294         status = "disabled";
 295         ranges = <0 0 0x08000000 0x01000000>;   /* minimum GPMC partition = 16MB */
 296         nand@0,0 {
 297                 /* To use NAND, DIP switch SW5 must be set like so:
 298                  * SW5.1 (NAND_SELn) = ON (LOW)
 299                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 300                  */
 301                 compatible = "ti,omap2-nand";
 302                 reg = <0 0 4>;          /* device IO registers */
 303                 interrupt-parent = <&gpmc>;
 304                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 305                              <1 IRQ_TYPE_NONE>; /* termcount */
 306                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */     /* device IO registers */
 307                 ti,nand-ecc-opt = "bch8";
 308                 ti,elm-id = <&elm>;
 309                 nand-bus-width = <16>;
 310                 gpmc,device-width = <2>;
 311                 gpmc,sync-clk-ps = <0>;
 312                 gpmc,cs-on-ns = <0>;
 313                 gpmc,cs-rd-off-ns = <80>;
 314                 gpmc,cs-wr-off-ns = <80>;
 315                 gpmc,adv-on-ns = <0>;
 316                 gpmc,adv-rd-off-ns = <60>;
 317                 gpmc,adv-wr-off-ns = <60>;
 318                 gpmc,we-on-ns = <10>;
 319                 gpmc,we-off-ns = <50>;
 320                 gpmc,oe-on-ns = <4>;
 321                 gpmc,oe-off-ns = <40>;
 322                 gpmc,access-ns = <40>;
 323                 gpmc,wr-access-ns = <80>;
 324                 gpmc,rd-cycle-ns = <80>;
 325                 gpmc,wr-cycle-ns = <80>;
 326                 gpmc,bus-turnaround-ns = <0>;
 327                 gpmc,cycle2cycle-delay-ns = <0>;
 328                 gpmc,clk-activation-ns = <0>;
 329                 gpmc,wait-monitoring-ns = <0>;
 330                 gpmc,wr-data-mux-bus-ns = <0>;
 331                 /* MTD partition table */
 332                 /* All SPL-* partitions are sized to minimal length
 333                  * which can be independently programmable. For
 334                  * NAND flash this is equal to size of erase-block */
 335                 #address-cells = <1>;
 336                 #size-cells = <1>;
 337                 partition@0 {
 338                         label = "NAND.SPL";
 339                         reg = <0x00000000 0x000020000>;
 340                 };
 341                 partition@1 {
 342                         label = "NAND.SPL.backup1";
 343                         reg = <0x00020000 0x00020000>;
 344                 };
 345                 partition@2 {
 346                         label = "NAND.SPL.backup2";
 347                         reg = <0x00040000 0x00020000>;
 348                 };
 349                 partition@3 {
 350                         label = "NAND.SPL.backup3";
 351                         reg = <0x00060000 0x00020000>;
 352                 };
 353                 partition@4 {
 354                         label = "NAND.u-boot-spl-os";
 355                         reg = <0x00080000 0x00040000>;
 356                 };
 357                 partition@5 {
 358                         label = "NAND.u-boot";
 359                         reg = <0x000c0000 0x00100000>;
 360                 };
 361                 partition@6 {
 362                         label = "NAND.u-boot-env";
 363                         reg = <0x001c0000 0x00020000>;
 364                 };
 365                 partition@7 {
 366                         label = "NAND.u-boot-env.backup1";
 367                         reg = <0x001e0000 0x00020000>;
 368                 };
 369                 partition@8 {
 370                         label = "NAND.kernel";
 371                         reg = <0x00200000 0x00800000>;
 372                 };
 373                 partition@9 {
 374                         label = "NAND.file-system";
 375                         reg = <0x00a00000 0x0f600000>;
 376                 };
 377         };
 378 };
 379
 380 &usb2_phy1 {
 381         phy-supply = <&ldo4_reg>;
 382 };
 383
 384 &usb2_phy2 {
 385         phy-supply = <&ldo4_reg>;
 386 };
 387
 388 &omap_dwc3_1 {
 389         extcon = <&extcon_usb1>;
 390 };
 391
 392 &omap_dwc3_2 {
 393         extcon = <&extcon_usb2>;
 394 };
 395
 396 &usb1 {
 397         dr_mode = "otg";
 398 };
 399
 400 &usb2 {
 401         dr_mode = "host";
 402 };
 403
 404 &mmc1 {
 405         status = "okay";
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&mmc1_pins_default>;
 408         vmmc_aux-supply = <&ldo1_reg>;
 409         bus-width = <4>;
 410         /*
 411          * SDCD signal is not being used here - using the fact that GPIO mode
 412          * is a viable alternative
 413          */
 414         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 415         max-frequency = <192000000>;
 416 };
 417
 418 &mmc2 {
 419         /* SW5-3 in ON position */
 420         status = "okay";
 421         pinctrl-names = "default";
 422         pinctrl-0 = <&mmc2_pins_default>;
 423
 424         vmmc-supply = <&evm_3v3>;
 425         bus-width = <8>;
 426         ti,non-removable;
 427         max-frequency = <192000000>;
 428 };
 429
 430 &mac {
 431         status = "okay";
 432 };
 433
 434 &dcan1 {
 435         status = "ok";
 436 };
 437
 438 &qspi {
 439         status = "okay";
 440
 441         spi-max-frequency = <76800000>;
 442         m25p80@0 {
 443                 compatible = "s25fl256s1", "spi-flash";
 444                 spi-max-frequency = <76800000>;
 445                 reg = <0>;
 446                 spi-tx-bus-width = <1>;
 447                 spi-rx-bus-width = <4>;
 448                 #address-cells = <1>;
 449                 #size-cells = <1>;
 450
 451                 /* MTD partition table.
 452                  * The ROM checks the first four physical blocks
 453                  * for a valid file to boot and the flash here is
 454                  * 64KiB block size.
 455                  */
 456                 partition@0 {
 457                         label = "QSPI.SPL";
 458                         reg = <0x00000000 0x000010000>;
 459                 };
 460                 partition@1 {
 461                         label = "QSPI.SPL.backup1";
 462                         reg = <0x00010000 0x00010000>;
 463                 };
 464                 partition@2 {
 465                         label = "QSPI.SPL.backup2";
 466                         reg = <0x00020000 0x00010000>;
 467                 };
 468                 partition@3 {
 469                         label = "QSPI.SPL.backup3";
 470                         reg = <0x00030000 0x00010000>;
 471                 };
 472                 partition@4 {
 473                         label = "QSPI.u-boot";
 474                         reg = <0x00040000 0x00100000>;
 475                 };
 476                 partition@5 {
 477                         label = "QSPI.u-boot-spl-os";
 478                         reg = <0x00140000 0x00080000>;
 479                 };
 480                 partition@6 {
 481                         label = "QSPI.u-boot-env";
 482                         reg = <0x001c0000 0x00010000>;
 483                 };
 484                 partition@7 {
 485                         label = "QSPI.u-boot-env.backup1";
 486                         reg = <0x001d0000 0x0010000>;
 487                 };
 488                 partition@8 {
 489                         label = "QSPI.kernel";
 490                         reg = <0x001e0000 0x0800000>;
 491                 };
 492                 partition@9 {
 493                         label = "QSPI.file-system";
 494                         reg = <0x009e0000 0x01620000>;
 495                 };
 496         };
 497 };
 498
 499 &dss {
 500         status = "ok";
 501
 502         vdda_video-supply = <&ldo5_reg>;
 503 };
 504
 505 &hdmi {
 506         status = "ok";
 507
 508         port {
 509                 hdmi_out: endpoint {
 510                         remote-endpoint = <&tpd12s015_in>;
 511                 };
 512         };
 513 };