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1 /*
2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 /dts-v1/;
9
10 #include "dra72x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14         model = "TI DRA722";
15         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
16
17         chosen {
18                 stdout-path = &uart1;
19                 tick-timer = &timer2;
20         };
21
22         memory {
23                 device_type = "memory";
24                 reg = <0x80000000 0x40000000>; /* 1024 MB */
25         };
26
27         aliases {
28                 display0 = &hdmi0;
29         };
30
31         evm_3v3: fixedregulator-evm_3v3 {
32                 compatible = "regulator-fixed";
33                 regulator-name = "evm_3v3";
34                 regulator-min-microvolt = <3300000>;
35                 regulator-max-microvolt = <3300000>;
36         };
37
38         extcon_usb1: extcon_usb1 {
39                 compatible = "linux,extcon-usb-gpio";
40                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
41         };
42
43         extcon_usb2: extcon_usb2 {
44                 compatible = "linux,extcon-usb-gpio";
45                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
46         };
47
48         hdmi0: connector {
49                 compatible = "hdmi-connector";
50                 label = "hdmi";
51
52                 type = "a";
53
54                 port {
55                         hdmi_connector_in: endpoint {
56                                 remote-endpoint = <&tpd12s015_out>;
57                         };
58                 };
59         };
60
61         tpd12s015: encoder {
62                 compatible = "ti,tpd12s015";
63
64                 pinctrl-names = "default";
65                 pinctrl-0 = <&tpd12s015_pins>;
66
67                 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
68                         <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
69                         <&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
70
71                 ports {
72                         #address-cells = <1>;
73                         #size-cells = <0>;
74
75                         port@0 {
76                                 reg = <0>;
77
78                                 tpd12s015_in: endpoint {
79                                         remote-endpoint = <&hdmi_out>;
80                                 };
81                         };
82
83                         port@1 {
84                                 reg = <1>;
85
86                                 tpd12s015_out: endpoint {
87                                         remote-endpoint = <&hdmi_connector_in>;
88                                 };
89                         };
90                 };
91         };
92 };
93
94 &dra7_pmx_core {
95         i2c1_pins: pinmux_i2c1_pins {
96                 pinctrl-single,pins = <
97                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
98                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
99                 >;
100         };
101
102         i2c5_pins: pinmux_i2c5_pins {
103                 pinctrl-single,pins = <
104                         0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
105                         0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
106                 >;
107         };
108
109         nand_default: nand_default {
110                 pinctrl-single,pins = <
111                         0x0     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
112                         0x4     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
113                         0x8     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
114                         0xc     (PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
115                         0x10    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
116                         0x14    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
117                         0x18    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
118                         0x1c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
119                         0x20    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
120                         0x24    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
121                         0x28    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
122                         0x2c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
123                         0x30    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
124                         0x34    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
125                         0x38    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
126                         0x3c    (PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
127                         0xb4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
128                         0xc4    (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
129                         0xcc    (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
130                         0xc8    (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
131                         0xd0    (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
132                         0xd8    (PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
133                 >;
134         };
135
136         usb1_pins: pinmux_usb1_pins {
137                 pinctrl-single,pins = <
138                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
139                 >;
140         };
141
142         usb2_pins: pinmux_usb2_pins {
143                 pinctrl-single,pins = <
144                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
145                 >;
146         };
147
148         tps65917_pins_default: tps65917_pins_default {
149                 pinctrl-single,pins = <
150                         0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
151                 >;
152         };
153
154         mmc1_pins_default: mmc1_pins_default {
155                 pinctrl-single,pins = <
156                         0x36c (PIN_INPUT | MUX_MODE14)  /* mmc1sdcd.gpio219 */
157                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
158                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
159                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
160                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
161                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
162                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
163                 >;
164         };
165
166         mmc2_pins_default: mmc2_pins_default {
167                 pinctrl-single,pins = <
168                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
169                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
170                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
171                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
172                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
173                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
174                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
175                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
176                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
177                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
178                 >;
179         };
180
181         dcan1_pins_default: dcan1_pins_default {
182                 pinctrl-single,pins = <
183                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
184                         0x418   (PULL_UP | MUX_MODE1)   /* wakeup0.dcan1_rx */
185                 >;
186         };
187
188         dcan1_pins_sleep: dcan1_pins_sleep {
189                 pinctrl-single,pins = <
190                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
191                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
192                 >;
193         };
194
195         qspi1_pins: pinmux_qspi1_pins {
196                 pinctrl-single,pins = <
197                         0x74 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_a13.qspi1_rtclk */
198                         0x78 (PIN_INPUT | MUX_MODE1)    /* gpmc_a14.qspi1_d3 */
199                         0x7c (PIN_INPUT | MUX_MODE1)    /* gpmc_a15.qspi1_d2 */
200                         0x80 (PIN_INPUT | MUX_MODE1)    /* gpmc_a16.qspi1_d1 */
201                         0x84 (PIN_INPUT | MUX_MODE1)    /* gpmc_a17.qspi1_d0 */
202                         0x88 (PIN_OUTPUT | MUX_MODE1)   /* qpmc_a18.qspi1_sclk */
203                         0xb8 (PIN_OUTPUT | MUX_MODE1)   /* gpmc_cs2.qspi1_cs0 */
204                 >;
205         };
206
207         hdmi_pins: pinmux_hdmi_pins {
208                 pinctrl-single,pins = <
209                         0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
210                         0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
211                 >;
212         };
213
214         tpd12s015_pins: pinmux_tpd12s015_pins {
215                 pinctrl-single,pins = <
216                         0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
217                 >;
218         };
219 };
220
221 &i2c1 {
222         status = "okay";
223         pinctrl-names = "default";
224         pinctrl-0 = <&i2c1_pins>;
225         clock-frequency = <400000>;
226
227         tps65917: tps65917@58 {
228                 compatible = "ti,tps65917";
229                 reg = <0x58>;
230
231                 pinctrl-names = "default";
232                 pinctrl-0 = <&tps65917_pins_default>;
233
234                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
235                 interrupt-controller;
236                 #interrupt-cells = <2>;
237
238                 ti,system-power-controller;
239
240                 tps65917_pmic {
241                         compatible = "ti,tps65917-pmic";
242
243                         regulators {
244                                 smps1_reg: smps1 {
245                                         /* VDD_MPU */
246                                         regulator-name = "smps1";
247                                         regulator-min-microvolt = <850000>;
248                                         regulator-max-microvolt = <1250000>;
249                                         regulator-always-on;
250                                         regulator-boot-on;
251                                 };
252
253                                 smps2_reg: smps2 {
254                                         /* VDD_CORE */
255                                         regulator-name = "smps2";
256                                         regulator-min-microvolt = <850000>;
257                                         regulator-max-microvolt = <1060000>;
258                                         regulator-boot-on;
259                                         regulator-always-on;
260                                 };
261
262                                 smps3_reg: smps3 {
263                                         /* VDD_GPU IVA DSPEVE */
264                                         regulator-name = "smps3";
265                                         regulator-min-microvolt = <850000>;
266                                         regulator-max-microvolt = <1250000>;
267                                         regulator-boot-on;
268                                         regulator-always-on;
269                                 };
270
271                                 smps4_reg: smps4 {
272                                         /* VDDS1V8 */
273                                         regulator-name = "smps4";
274                                         regulator-min-microvolt = <1800000>;
275                                         regulator-max-microvolt = <1800000>;
276                                         regulator-always-on;
277                                         regulator-boot-on;
278                                 };
279
280                                 smps5_reg: smps5 {
281                                         /* VDD_DDR */
282                                         regulator-name = "smps5";
283                                         regulator-min-microvolt = <1350000>;
284                                         regulator-max-microvolt = <1350000>;
285                                         regulator-boot-on;
286                                         regulator-always-on;
287                                 };
288
289                                 ldo1_reg: ldo1 {
290                                         /* LDO1_OUT --> SDIO  */
291                                         regulator-name = "ldo1";
292                                         regulator-min-microvolt = <1800000>;
293                                         regulator-max-microvolt = <3300000>;
294                                         regulator-boot-on;
295                                 };
296
297                                 ldo2_reg: ldo2 {
298                                         /* LDO2_OUT --> TP1017 (UNUSED)  */
299                                         regulator-name = "ldo2";
300                                         regulator-min-microvolt = <1800000>;
301                                         regulator-max-microvolt = <3300000>;
302                                 };
303
304                                 ldo3_reg: ldo3 {
305                                         /* VDDA_1V8_PHY */
306                                         regulator-name = "ldo3";
307                                         regulator-min-microvolt = <1800000>;
308                                         regulator-max-microvolt = <1800000>;
309                                         regulator-boot-on;
310                                         regulator-always-on;
311                                 };
312
313                                 ldo5_reg: ldo5 {
314                                         /* VDDA_1V8_PLL */
315                                         regulator-name = "ldo5";
316                                         regulator-min-microvolt = <1800000>;
317                                         regulator-max-microvolt = <1800000>;
318                                         regulator-always-on;
319                                         regulator-boot-on;
320                                 };
321
322                                 ldo4_reg: ldo4 {
323                                         /* VDDA_3V_USB: VDDA_USBHS33 */
324                                         regulator-name = "ldo4";
325                                         regulator-min-microvolt = <3300000>;
326                                         regulator-max-microvolt = <3300000>;
327                                         regulator-boot-on;
328                                 };
329                         };
330                 };
331
332                 tps65917_power_button {
333                         compatible = "ti,palmas-pwrbutton";
334                         interrupt-parent = <&tps65917>;
335                         interrupts = <1 IRQ_TYPE_NONE>;
336                         wakeup-source;
337                         ti,palmas-long-press-seconds = <6>;
338                 };
339         };
340
341         pcf_gpio_21: gpio@21 {
342                 compatible = "ti,pcf8575";
343                 reg = <0x21>;
344                 lines-initial-states = <0x1408>;
345                 gpio-controller;
346                 #gpio-cells = <2>;
347                 interrupt-parent = <&gpio6>;
348                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
349                 interrupt-controller;
350                 #interrupt-cells = <2>;
351         };
352 };
353
354 &i2c5 {
355         status = "okay";
356         pinctrl-names = "default";
357         pinctrl-0 = <&i2c5_pins>;
358         clock-frequency = <400000>;
359
360         pcf_hdmi: pcf8575@26 {
361                 compatible = "nxp,pcf8575";
362                 reg = <0x26>;
363                 gpio-controller;
364                 #gpio-cells = <2>;
365                 /*
366                  * initial state is used here to keep the mdio interface
367                  * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
368                  * VIN2_S0 driven high otherwise Ethernet stops working
369                  * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
370                  */
371                 lines-initial-states = <0x0f2b>;
372         };
373 };
374
375 &uart1 {
376         status = "okay";
377 };
378
379 &elm {
380         status = "okay";
381 };
382
383 &gpmc {
384         status = "okay";
385         pinctrl-names = "default";
386         pinctrl-0 = <&nand_default>;
387         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
388         nand@0,0 {
389                 /* To use NAND, DIP switch SW5 must be set like so:
390                  * SW5.1 (NAND_SELn) = ON (LOW)
391                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
392                  */
393                 reg = <0 0 4>;          /* device IO registers */
394                 ti,nand-ecc-opt = "bch8";
395                 ti,elm-id = <&elm>;
396                 nand-bus-width = <16>;
397                 gpmc,device-width = <2>;
398                 gpmc,sync-clk-ps = <0>;
399                 gpmc,cs-on-ns = <0>;
400                 gpmc,cs-rd-off-ns = <80>;
401                 gpmc,cs-wr-off-ns = <80>;
402                 gpmc,adv-on-ns = <0>;
403                 gpmc,adv-rd-off-ns = <60>;
404                 gpmc,adv-wr-off-ns = <60>;
405                 gpmc,we-on-ns = <10>;
406                 gpmc,we-off-ns = <50>;
407                 gpmc,oe-on-ns = <4>;
408                 gpmc,oe-off-ns = <40>;
409                 gpmc,access-ns = <40>;
410                 gpmc,wr-access-ns = <80>;
411                 gpmc,rd-cycle-ns = <80>;
412                 gpmc,wr-cycle-ns = <80>;
413                 gpmc,bus-turnaround-ns = <0>;
414                 gpmc,cycle2cycle-delay-ns = <0>;
415                 gpmc,clk-activation-ns = <0>;
416                 gpmc,wait-monitoring-ns = <0>;
417                 gpmc,wr-data-mux-bus-ns = <0>;
418                 /* MTD partition table */
419                 /* All SPL-* partitions are sized to minimal length
420                  * which can be independently programmable. For
421                  * NAND flash this is equal to size of erase-block */
422                 #address-cells = <1>;
423                 #size-cells = <1>;
424                 partition@0 {
425                         label = "NAND.SPL";
426                         reg = <0x00000000 0x000020000>;
427                 };
428                 partition@1 {
429                         label = "NAND.SPL.backup1";
430                         reg = <0x00020000 0x00020000>;
431                 };
432                 partition@2 {
433                         label = "NAND.SPL.backup2";
434                         reg = <0x00040000 0x00020000>;
435                 };
436                 partition@3 {
437                         label = "NAND.SPL.backup3";
438                         reg = <0x00060000 0x00020000>;
439                 };
440                 partition@4 {
441                         label = "NAND.u-boot-spl-os";
442                         reg = <0x00080000 0x00040000>;
443                 };
444                 partition@5 {
445                         label = "NAND.u-boot";
446                         reg = <0x000c0000 0x00100000>;
447                 };
448                 partition@6 {
449                         label = "NAND.u-boot-env";
450                         reg = <0x001c0000 0x00020000>;
451                 };
452                 partition@7 {
453                         label = "NAND.u-boot-env.backup1";
454                         reg = <0x001e0000 0x00020000>;
455                 };
456                 partition@8 {
457                         label = "NAND.kernel";
458                         reg = <0x00200000 0x00800000>;
459                 };
460                 partition@9 {
461                         label = "NAND.file-system";
462                         reg = <0x00a00000 0x0f600000>;
463                 };
464         };
465 };
466
467 &usb2_phy1 {
468         phy-supply = <&ldo4_reg>;
469 };
470
471 &usb2_phy2 {
472         phy-supply = <&ldo4_reg>;
473 };
474
475 &omap_dwc3_1 {
476         extcon = <&extcon_usb1>;
477 };
478
479 &omap_dwc3_2 {
480         extcon = <&extcon_usb2>;
481 };
482
483 &usb1 {
484         dr_mode = "peripheral";
485         pinctrl-names = "default";
486         pinctrl-0 = <&usb1_pins>;
487 };
488
489 &usb2 {
490         dr_mode = "host";
491         pinctrl-names = "default";
492         pinctrl-0 = <&usb2_pins>;
493 };
494
495 &mmc1 {
496         status = "okay";
497         pinctrl-names = "default";
498         pinctrl-0 = <&mmc1_pins_default>;
499
500         vmmc-supply = <&ldo1_reg>;
501         bus-width = <4>;
502         /*
503          * SDCD signal is not being used here - using the fact that GPIO mode
504          * is a viable alternative
505          */
506         cd-gpios = <&gpio6 27 0>;
507 };
508
509 &mmc2 {
510         /* SW5-3 in ON position */
511         status = "okay";
512         pinctrl-names = "default";
513         pinctrl-0 = <&mmc2_pins_default>;
514
515         vmmc-supply = <&evm_3v3>;
516         bus-width = <8>;
517         ti,non-removable;
518 };
519
520 &dra7_pmx_core {
521         cpsw_default: cpsw_default {
522                 pinctrl-single,pins = <
523                         /* Slave 2 */
524                         0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
525                         0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
526                         0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
527                         0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
528                         0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
529                         0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
530                         0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
531                         0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
532                         0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
533                         0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
534                         0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
535                         0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
536                 >;
537
538         };
539
540         cpsw_sleep: cpsw_sleep {
541                 pinctrl-single,pins = <
542                         /* Slave 2 */
543                         0x198 (MUX_MODE15)
544                         0x19c (MUX_MODE15)
545                         0x1a0 (MUX_MODE15)
546                         0x1a4 (MUX_MODE15)
547                         0x1a8 (MUX_MODE15)
548                         0x1ac (MUX_MODE15)
549                         0x1b0 (MUX_MODE15)
550                         0x1b4 (MUX_MODE15)
551                         0x1b8 (MUX_MODE15)
552                         0x1bc (MUX_MODE15)
553                         0x1c0 (MUX_MODE15)
554                         0x1c4 (MUX_MODE15)
555                 >;
556         };
557
558         davinci_mdio_default: davinci_mdio_default {
559                 pinctrl-single,pins = <
560                         /* MDIO */
561                         0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
562                         0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
563                 >;
564         };
565
566         davinci_mdio_sleep: davinci_mdio_sleep {
567                 pinctrl-single,pins = <
568                         0x23c (MUX_MODE15)
569                         0x240 (MUX_MODE15)
570                 >;
571         };
572 };
573
574 &mac {
575         status = "okay";
576         pinctrl-names = "default", "sleep";
577         pinctrl-0 = <&cpsw_default>;
578         pinctrl-1 = <&cpsw_sleep>;
579 };
580
581 &cpsw_emac1 {
582         phy_id = <&davinci_mdio>, <3>;
583         phy-mode = "rgmii";
584 };
585
586 &davinci_mdio {
587         pinctrl-names = "default", "sleep";
588         pinctrl-0 = <&davinci_mdio_default>;
589         pinctrl-1 = <&davinci_mdio_sleep>;
590         active_slave = <1>;
591 };
592
593 &dcan1 {
594         status = "ok";
595         pinctrl-names = "default", "sleep", "active";
596         pinctrl-0 = <&dcan1_pins_sleep>;
597         pinctrl-1 = <&dcan1_pins_sleep>;
598         pinctrl-2 = <&dcan1_pins_default>;
599 };
600
601 &qspi {
602         status = "okay";
603         pinctrl-names = "default";
604         pinctrl-0 = <&qspi1_pins>;
605
606         spi-max-frequency = <48000000>;
607         m25p80@0 {
608                 compatible = "s25fl256s1","spi-flash";
609                 spi-max-frequency = <48000000>;
610                 reg = <0>;
611                 spi-tx-bus-width = <1>;
612                 spi-rx-bus-width = <4>;
613                 spi-cpol;
614                 spi-cpha;
615                 #address-cells = <1>;
616                 #size-cells = <1>;
617
618                 /* MTD partition table.
619                  * The ROM checks the first four physical blocks
620                  * for a valid file to boot and the flash here is
621                  * 64KiB block size.
622                  */
623                 partition@0 {
624                         label = "QSPI.SPL";
625                         reg = <0x00000000 0x000010000>;
626                 };
627                 partition@1 {
628                         label = "QSPI.SPL.backup1";
629                         reg = <0x00010000 0x00010000>;
630                 };
631                 partition@2 {
632                         label = "QSPI.SPL.backup2";
633                         reg = <0x00020000 0x00010000>;
634                 };
635                 partition@3 {
636                         label = "QSPI.SPL.backup3";
637                         reg = <0x00030000 0x00010000>;
638                 };
639                 partition@4 {
640                         label = "QSPI.u-boot";
641                         reg = <0x00040000 0x00100000>;
642                 };
643                 partition@5 {
644                         label = "QSPI.u-boot-spl-os";
645                         reg = <0x00140000 0x00080000>;
646                 };
647                 partition@6 {
648                         label = "QSPI.u-boot-env";
649                         reg = <0x001c0000 0x00010000>;
650                 };
651                 partition@7 {
652                         label = "QSPI.u-boot-env.backup1";
653                         reg = <0x001d0000 0x0010000>;
654                 };
655                 partition@8 {
656                         label = "QSPI.kernel";
657                         reg = <0x001e0000 0x0800000>;
658                 };
659                 partition@9 {
660                         label = "QSPI.file-system";
661                         reg = <0x009e0000 0x01620000>;
662                 };
663         };
664 };
665
666 &dss {
667         status = "ok";
668
669         vdda_video-supply = <&ldo5_reg>;
670 };
671
672 &hdmi {
673         status = "ok";
674         vdda-supply = <&ldo3_reg>;
675
676         pinctrl-names = "default";
677         pinctrl-0 = <&hdmi_pins>;
678
679         port {
680                 hdmi_out: endpoint {
681                         remote-endpoint = <&tpd12s015_in>;
682                 };
683         };
684 };