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1 /*
2  * SAMSUNG/GOOGLE Peach-Pit board device tree source
3  *
4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5  *              http://www.samsung.com
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 /dts-v1/;
11 #include "exynos54xx.dtsi"
12
13 / {
14         model = "Samsung/Google Peach Pit board based on Exynos5420";
15
16         compatible = "google,pit-rev#", "google,pit",
17                 "google,peach", "samsung,exynos5420", "samsung,exynos5";
18
19         config {
20                 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
21                 hwid = "PIT TEST A-A 7848";
22                 lazy-init = <1>;
23         };
24
25         aliases {
26                 serial0 = "/serial@12C30000";
27                 console = "/serial@12C30000";
28                 pmic = "/i2c@12CA0000";
29                 i2c104 = &i2c_tunnel;
30         };
31
32         dmc {
33                 mem-manuf = "samsung";
34                 mem-type = "ddr3";
35                 clock-frequency = <800000000>;
36                 arm-frequency = <900000000>;
37         };
38
39         tmu@10060000 {
40                 samsung,min-temp        = <25>;
41                 samsung,max-temp        = <125>;
42                 samsung,start-warning   = <95>;
43                 samsung,start-tripping  = <105>;
44                 samsung,hw-tripping     = <110>;
45                 samsung,efuse-min-value = <40>;
46                 samsung,efuse-value     = <55>;
47                 samsung,efuse-max-value = <100>;
48                 samsung,slope           = <274761730>;
49                 samsung,dc-value        = <25>;
50         };
51
52         /* MAX77802 is on i2c bus 4 */
53         i2c@12CA0000 {
54                 clock-frequency = <400000>;
55                 power-regulator@9 {
56                         compatible = "maxim,max77802-pmic";
57                         reg = <0x9>;
58                 };
59         };
60
61         i2c@12CD0000 { /* i2c7 */
62                 clock-frequency = <100000>;
63                soundcodec@20 {
64                       reg = <0x20>;
65                       compatible = "maxim,max98090-codec";
66                };
67
68                 edp-lvds-bridge@48 {
69                         compatible = "parade,ps8625";
70                         reg = <0x48>;
71                         sleep-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
72                         reset-gpios = <&gpy7 7 GPIO_ACTIVE_LOW>;
73                         parade,regs = /bits/ 8 <
74                                 0x02 0xa1 0x01  /* HPD low */
75                                 /*
76                                 * SW setting
77                                 * [1:0] SW output 1.2V voltage is lower to 96%
78                                 */
79                                 0x04 0x14 0x01
80                                 /*
81                                 * RCO SS setting
82                                 * [5:4] = b01 0.5%, b10 1%, b11 1.5%
83                                 */
84                                 0x04 0xe3 0x20
85                                 0x04 0xe2 0x80 /* [7] RCO SS enable */
86                                 /*
87                                 *  RPHY Setting
88                                 * [3:2] CDR tune wait cycle before
89                                 * measure for fine tune b00: 1us,
90                                 * 01: 0.5us, 10:2us, 11:4us.
91                                 */
92                                 0x04 0x8a 0x0c
93                                 0x04 0x89 0x08 /* [3] RFD always on */
94                                 /*
95                                 * CTN lock in/out:
96                                 * 20000ppm/80000ppm. Lock out 2
97                                 * times.
98                                 */
99                                 0x04 0x71 0x2d
100                                 /*
101                                 * 2.7G CDR settings
102                                 * NOF=40LSB for HBR CDR setting
103                                 */
104                                 0x04 0x7d 0x07
105                                 0x04 0x7b 0x00  /* [1:0] Fmin=+4bands */
106                                 0x04 0x7a 0xfd  /* [7:5] DCO_FTRNG=+-40% */
107                                 /*
108                                 * 1.62G CDR settings
109                                 * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
110                                 */
111                                 0x04 0xc0 0x12
112                                 0x04 0xc1 0x92  /* Gitune=-37% */
113                                 0x04 0xc2 0x1c  /* Fbstep=100% */
114                                 0x04 0x32 0x80  /* [7]LOS signal disable */
115                                 /*
116                                 * RPIO Setting
117                                 * [7:4] LVDS driver bias current :
118                                 * 75% (250mV swing)
119                                 */
120                                 0x04 0x00 0xb0
121                                 /*
122                                 * [7:6] Right-bar GPIO output strength is 8mA
123                                 */
124                                 0x04 0x15 0x40
125                                 /* EQ Training State Machine Setting */
126                                 0x04 0x54 0x10  /* RCO calibration start */
127                                 /* [4:0] MAX_LANE_COUNT set to one lane */
128                                 0x01 0x02 0x81
129                                 /* [4:0] LANE_COUNT_SET set to one lane */
130                                 0x01 0x21 0x81
131                                 0x00 0x52 0x20
132                                 0x00 0xf1 0x03  /* HPD CP toggle enable */
133                                 0x00 0x62 0x41
134                                 /* Counter number add 1ms counter delay */
135                                 0x00 0xf6 0x01
136                                 /*
137                                 * [6]PWM function control by
138                                 * DPCD0040f[7], default is PWM
139                                 * block always works.
140                                 */
141                                 0x00 0x77 0x06
142                                 /*
143                                 * 04h Adjust VTotal tolerance to
144                                 * fix the 30Hz no display issue
145                                 */
146                                 0x00 0x4c 0x04
147                                 /* DPCD00400='h00, Parade OUI = 'h001cf8 */
148                                 0x01 0xc0 0x00
149                                 0x01 0xc1 0x1c  /* DPCD00401='h1c */
150                                 0x01 0xc2 0xf8  /* DPCD00402='hf8 */
151                                 /*
152                                 * DPCD403~408 = ASCII code
153                                 * D2SLV5='h4432534c5635
154                                 */
155                                 0x01 0xc3 0x44
156                                 0x01 0xc4 0x32  /* DPCD404 */
157                                 0x01 0xc5 0x53  /* DPCD405 */
158                                 0x01 0xc6 0x4c  /* DPCD406 */
159                                 0x01 0xc7 0x56  /* DPCD407 */
160                                 0x01 0xc8 0x35  /* DPCD408 */
161                                 /*
162                                 * DPCD40A, Initial Code major  revision
163                                 * '01'
164                                 */
165                                 0x01 0xca 0x01
166                                 /* DPCD40B Initial Code minor revision '05' */
167                                 0x01 0xcb 0x05
168                                 /* DPCD720 Select internal PWM */
169                                 0x01 0xa5 0xa0
170                                 /*
171                                 * FFh for 100% PWM of brightness, 0h for 0%
172                                 * brightness
173                                 */
174                                 0x01 0xa7 0xff
175                                 /*
176                                 * Set LVDS output as 6bit-VESA mapping,
177                                 * single LVDS channel
178                                 */
179                                 0x01 0xcc 0x13
180                                 /* Enable SSC set by register */
181                                 0x02 0xb1 0x20
182                                 /*
183                                 * Set SSC enabled and +/-1% central
184                                 * spreading
185                                 */
186                                 0x04 0x10 0x16
187                                 /* MPU Clock source: LC => RCO */
188                                 0x04 0x59 0x60
189                                 0x04 0x54 0x14  /* LC -> RCO */
190                                 0x02 0xa1 0x91>;  /* HPD high */
191                 };
192         };
193
194         sound@3830000 {
195                 samsung,codec-type = "max98090";
196         };
197
198         i2c@12E10000 { /* i2c9 */
199                 clock-frequency = <400000>;
200                 tpm@20 {
201                         compatible = "infineon,slb9645tt";
202                         reg = <0x20>;
203                 };
204         };
205
206         spi@12d30000 { /* spi1 */
207                 spi-max-frequency = <50000000>;
208                 firmware_storage_spi: flash@0 {
209                         compatible = "spi-flash";
210                         reg = <0>;
211
212                         /*
213                          * A region for the kernel to store a panic event
214                          * which the firmware will add to the log.
215                         */
216                         elog-panic-event-offset = <0x01e00000 0x100000>;
217
218                         elog-shrink-size = <0x400>;
219                         elog-full-threshold = <0xc00>;
220                 };
221         };
222
223         xhci@12000000 {
224                 samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
225         };
226
227         xhci@12400000 {
228                 samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
229         };
230
231         fimd@14400000 {
232                 samsung,vl-freq = <60>;
233                 samsung,vl-col = <1366>;
234                 samsung,vl-row = <768>;
235                 samsung,vl-width = <1366>;
236                 samsung,vl-height = <768>;
237
238                 samsung,vl-clkp;
239                 samsung,vl-dp;
240                 samsung,vl-bpix = <4>;
241
242                 samsung,vl-hspw = <32>;
243                 samsung,vl-hbpd = <40>;
244                 samsung,vl-hfpd = <40>;
245                 samsung,vl-vspw = <6>;
246                 samsung,vl-vbpd = <10>;
247                 samsung,vl-vfpd = <12>;
248                 samsung,vl-cmd-allow-len = <0xf>;
249
250                 samsung,winid = <3>;
251                 samsung,interface-mode = <1>;
252                 samsung,dp-enabled = <1>;
253                 samsung,dual-lcd-enabled = <0>;
254         };
255 };
256
257 &spi_2 {
258         spi-max-frequency = <3125000>;
259         spi-deactivate-delay = <200>;
260         status = "okay";
261         num-cs = <1>;
262         samsung,spi-src-clk = <0>;
263         cs-gpios = <&gpb1 2 0>;
264
265         cros_ec: cros-ec@0 {
266                 compatible = "google,cros-ec-spi";
267                 interrupt-parent = <&gpx1>;
268                 interrupts = <5 0>;
269                 reg = <0>;
270                 spi-half-duplex;
271                 spi-max-timeout-ms = <1100>;
272                 ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
273                 #address-cells = <1>;
274                 #size-cells = <1>;
275
276                 /*
277                  * This describes the flash memory within the EC. Note
278                  * that the STM32L flash erases to 0, not 0xff.
279                  */
280                 flash@8000000 {
281                         reg = <0x08000000 0x20000>;
282                         erase-value = <0>;
283                 };
284
285                 controller-data {
286                         samsung,spi-feedback-delay = <1>;
287                 };
288
289                 i2c_tunnel: i2c-tunnel {
290                         compatible = "google,cros-ec-i2c-tunnel";
291                         #address-cells = <1>;
292                         #size-cells = <0>;
293                         google,remote-bus = <0>;
294
295                         battery: sbs-battery@b {
296                                 compatible = "sbs,sbs-battery";
297                                 reg = <0xb>;
298                                 sbs,poll-retry-count = <1>;
299                                 sbs,i2c-retry-count = <2>;
300                         };
301
302                         power-regulator@48 {
303                                 compatible = "ti,tps65090";
304                                 reg = <0x48>;
305
306                                 regulators {
307                                         tps65090_dcdc1: dcdc1 {
308                                                 ti,enable-ext-control;
309                                         };
310                                         tps65090_dcdc2: dcdc2 {
311                                                 ti,enable-ext-control;
312                                         };
313                                         tps65090_dcdc3: dcdc3 {
314                                                 ti,enable-ext-control;
315                                         };
316                                         tps65090_fet1: fet1 {
317                                                 regulator-name = "vcd_led";
318                                         };
319                                         tps65090_fet2: fet2 {
320                                                 regulator-name = "video_mid";
321                                                 regulator-always-on;
322                                         };
323                                         tps65090_fet3: fet3 {
324                                                 regulator-name = "wwan_r";
325                                                 regulator-always-on;
326                                         };
327                                         tps65090_fet4: fet4 {
328                                                 regulator-name = "sdcard";
329                                                 regulator-always-on;
330                                         };
331                                         tps65090_fet5: fet5 {
332                                                 regulator-name = "camout";
333                                                 regulator-always-on;
334                                         };
335                                         tps65090_fet6: fet6 {
336                                                 regulator-name = "lcd_vdd";
337                                         };
338                                         tps65090_fet7: fet7 {
339                                                 regulator-name = "video_mid_1a";
340                                                 regulator-always-on;
341                                         };
342                                         tps65090_ldo1: ldo1 {
343                                         };
344                                         tps65090_ldo2: ldo2 {
345                                         };
346                                 };
347
348                                 charger {
349                                         compatible = "ti,tps65090-charger";
350                                 };
351                         };
352                 };
353         };
354 };
355
356 #include "cros-ec-keyboard.dtsi"