2 * Copyright 2016 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 /include/ "skeleton64.dtsi"
10 compatible = "fsl,ls1012a";
11 interrupt-parent = <&gic>;
14 compatible = "fixed-clock";
16 clock-frequency = <100000000>;
17 clock-output-names = "sysclk";
20 gic: interrupt-controller@1400000 {
21 compatible = "arm,gic-400";
22 #interrupt-cells = <3>;
24 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
25 <0x0 0x1402000 0 0x2000>, /* GICC */
26 <0x0 0x1404000 0 0x2000>, /* GICH */
27 <0x0 0x1406000 0 0x2000>; /* GICV */
28 interrupts = <1 9 0xf08>;
32 compatible = "simple-bus";
37 clockgen: clocking@1ee1000 {
38 compatible = "fsl,ls1012a-clockgen";
39 reg = <0x0 0x1ee1000 0x0 0x1000>;
45 compatible = "fsl,vf610-dspi";
48 reg = <0x0 0x2100000 0x0 0x10000>;
49 interrupts = <0 64 0x4>;
51 clocks = <&clockgen 4 0>;
59 compatible = "fsl,vf610-i2c";
62 reg = <0x0 0x2180000 0x0 0x10000>;
63 interrupts = <0 56 0x4>;
65 clocks = <&clockgen 4 0>;
70 compatible = "fsl,vf610-i2c";
73 reg = <0x0 0x2190000 0x0 0x10000>;
74 interrupts = <0 57 0x4>;
76 clocks = <&clockgen 4 0>;
80 duart0: serial@21c0500 {
81 compatible = "fsl,ns16550", "ns16550a";
82 reg = <0x00 0x21c0500 0x0 0x100>;
83 interrupts = <0 54 0x4>;
84 clocks = <&clockgen 4 0>;
87 duart1: serial@21c0600 {
88 compatible = "fsl,ns16550", "ns16550a";
89 reg = <0x00 0x21c0600 0x0 0x100>;
90 interrupts = <0 54 0x4>;
91 clocks = <&clockgen 4 0>;
94 qspi: quadspi@1550000 {
95 compatible = "fsl,vf610-qspi";
98 reg = <0x0 0x1550000 0x0 0x10000>,
99 <0x0 0x40000000 0x0 0x4000000>;
100 reg-names = "QuadSPI", "QuadSPI-memory";