2 * Copyright 2016 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 /include/ "skeleton64.dtsi"
10 compatible = "fsl,ls1012a";
11 interrupt-parent = <&gic>;
18 compatible = "arm,cortex-a53";
20 clocks = <&clockgen 1 0>;
26 compatible = "fixed-clock";
28 clock-frequency = <100000000>;
29 clock-output-names = "sysclk";
32 gic: interrupt-controller@1400000 {
33 compatible = "arm,gic-400";
34 #interrupt-cells = <3>;
36 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
37 <0x0 0x1402000 0 0x2000>, /* GICC */
38 <0x0 0x1404000 0 0x2000>, /* GICH */
39 <0x0 0x1406000 0 0x2000>; /* GICV */
40 interrupts = <1 9 0xf08>;
44 compatible = "simple-bus";
49 clockgen: clocking@1ee1000 {
50 compatible = "fsl,ls1012a-clockgen";
51 reg = <0x0 0x1ee1000 0x0 0x1000>;
57 compatible = "fsl,vf610-dspi";
60 reg = <0x0 0x2100000 0x0 0x10000>;
61 interrupts = <0 64 0x4>;
63 clocks = <&clockgen 4 0>;
71 compatible = "fsl,vf610-i2c";
74 reg = <0x0 0x2180000 0x0 0x10000>;
75 interrupts = <0 56 0x4>;
77 clocks = <&clockgen 4 0>;
82 compatible = "fsl,vf610-i2c";
85 reg = <0x0 0x2190000 0x0 0x10000>;
86 interrupts = <0 57 0x4>;
88 clocks = <&clockgen 4 0>;
92 duart0: serial@21c0500 {
93 compatible = "fsl,ns16550", "ns16550a";
94 reg = <0x00 0x21c0500 0x0 0x100>;
95 interrupts = <0 54 0x4>;
96 clocks = <&clockgen 4 0>;
99 duart1: serial@21c0600 {
100 compatible = "fsl,ns16550", "ns16550a";
101 reg = <0x00 0x21c0600 0x0 0x100>;
102 interrupts = <0 54 0x4>;
103 clocks = <&clockgen 4 0>;
106 qspi: quadspi@1550000 {
107 compatible = "fsl,vf610-qspi";
108 #address-cells = <1>;
110 reg = <0x0 0x1550000 0x0 0x10000>,
111 <0x0 0x40000000 0x0 0x4000000>;
112 reg-names = "QuadSPI", "QuadSPI-memory";