git.sur5r.net Git - u-boot/blob - arch/arm/dts/fsl-ls1043a-qds.dtsi

   1 /*
   2  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
   3  *
   4  * Copyright (C) 2015, Freescale Semiconductor
   5  *
   6  * Mingkai Hu <Mingkai.hu@freescale.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 /include/ "fsl-ls1043a.dtsi"
  14
  15 / {
  16         model = "LS1043A QDS Board";
  17         aliases {
  18                 spi0 = &qspi;
  19                 spi1 = &dspi0;
  20         };
  21 };
  22
  23 &dspi0 {
  24         bus-num = <0>;
  25         status = "okay";
  26
  27         dflash0: n25q128a {
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30                 compatible = "spi-flash";
  31                 reg = <0>;
  32                 spi-max-frequency = <1000000>; /* input clock */
  33         };
  34
  35         dflash1: sst25wf040b {
  36                 #address-cells = <1>;
  37                 #size-cells = <1>;
  38                 compatible = "spi-flash";
  39                 spi-max-frequency = <3500000>;
  40                 reg = <1>;
  41         };
  42
  43         dflash2: en25s64 {
  44                 #address-cells = <1>;
  45                 #size-cells = <1>;
  46                 compatible = "spi-flash";
  47                 spi-max-frequency = <3500000>;
  48                 reg = <2>;
  49         };
  50 };
  51
  52 &qspi {
  53         bus-num = <0>;
  54         status = "okay";
  55
  56         qflash0: s25fl128s@0 {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 compatible = "spi-flash";
  60                 spi-max-frequency = <20000000>;
  61                 reg = <0>;
  62         };
  63 };
  64
  65 &i2c0 {
  66         status = "okay";
  67         pca9547@77 {
  68                 compatible = "philips,pca9547";
  69                 reg = <0x77>;
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 i2c@0 {
  74                         #address-cells = <1>;
  75                         #size-cells = <0>;
  76                         reg = <0x0>;
  77
  78                         rtc@68 {
  79                                 compatible = "dallas,ds3232";
  80                                 reg = <0x68>;
  81                                 /* IRQ10_B */
  82                                 interrupts = <0 150 0x4>;
  83                         };
  84                 };
  85
  86                 i2c@2 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         reg = <0x2>;
  90
  91                         ina220@40 {
  92                                 compatible = "ti,ina220";
  93                                 reg = <0x40>;
  94                                 shunt-resistor = <1000>;
  95                         };
  96
  97                         ina220@41 {
  98                                 compatible = "ti,ina220";
  99                                 reg = <0x41>;
 100                                 shunt-resistor = <1000>;
 101                         };
 102                 };
 103
 104                 i2c@3 {
 105                         #address-cells = <1>;
 106                         #size-cells = <0>;
 107                         reg = <0x3>;
 108
 109                         eeprom@56 {
 110                                 compatible = "at24,24c512";
 111                                 reg = <0x56>;
 112                         };
 113
 114                         eeprom@57 {
 115                                 compatible = "at24,24c512";
 116                                 reg = <0x57>;
 117                         };
 118
 119                         adt7461a@4c {
 120                                 compatible = "adt7461a";
 121                                 reg = <0x4c>;
 122                         };
 123                 };
 124         };
 125 };
 126
 127 &ifc {
 128         #address-cells = <2>;
 129         #size-cells = <1>;
 130         /* NOR, NAND Flashes and FPGA on board */
 131         ranges = <0x0 0x0 0x0 0x60000000 0x08000000
 132                   0x2 0x0 0x0 0x7e800000 0x00010000
 133                   0x3 0x0 0x0 0x7fb00000 0x00000100>;
 134         status = "okay";
 135
 136         nor@0,0 {
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 compatible = "cfi-flash";
 140                 reg = <0x0 0x0 0x8000000>;
 141                 bank-width = <2>;
 142                 device-width = <1>;
 143         };
 144
 145         nand@2,0 {
 146                 compatible = "fsl,ifc-nand";
 147                 #address-cells = <1>;
 148                 #size-cells = <1>;
 149                 reg = <0x1 0x0 0x10000>;
 150         };
 151
 152         fpga: board-control@3,0 {
 153                 #address-cells = <1>;
 154                 #size-cells = <1>;
 155                 compatible = "simple-bus";
 156                 reg = <0x3 0x0 0x0000100>;
 157                 bank-width = <1>;
 158                 device-width = <1>;
 159                 ranges = <0 3 0 0x100>;
 160         };
 161 };
 162
 163 &duart0 {
 164         status = "okay";
 165 };
 166
 167 &duart1 {
 168         status = "okay";
 169 };
 170
 171 &lpuart0 {
 172         status = "okay";
 173 };