]> git.sur5r.net Git - u-boot/blob - arch/arm/dts/fsl-ls1046a-qds.dtsi
arm: zynq: Add support for the topic-miamilite system-on-module
[u-boot] / arch / arm / dts / fsl-ls1046a-qds.dtsi
1 /*
2  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3  *
4  * Copyright (C) 2016, Freescale Semiconductor
5  *
6  * Mingkai Hu <Mingkai.hu@nxp.com>
7  *
8  * This file is licensed under the terms of the GNU General Public
9  * License version 2.  This program is licensed "as is" without any
10  * warranty of any kind, whether express or implied.
11  */
12
13 /include/ "fsl-ls1046a.dtsi"
14
15 / {
16         model = "LS1046A QDS Board";
17         aliases {
18                 spi0 = &qspi;
19                 spi1 = &dspi0;
20         };
21 };
22
23 &dspi0 {
24         bus-num = <0>;
25         status = "okay";
26
27         dflash0: n25q128a {
28                 #address-cells = <1>;
29                 #size-cells = <1>;
30                 compatible = "spi-flash";
31                 spi-max-frequency = <1000000>; /* input clock */
32                 spi-cpol;
33                 spi-cpha;
34                 reg = <0>;
35         };
36
37         dflash1: sst25wf040b {
38                 #address-cells = <1>;
39                 #size-cells = <1>;
40                 compatible = "spi-flash";
41                 spi-max-frequency = <3500000>;
42                 spi-cpol;
43                 spi-cpha;
44                 reg = <1>;
45         };
46
47         dflash2: en25s64 {
48                 #address-cells = <1>;
49                 #size-cells = <1>;
50                 compatible = "spi-flash";
51                 spi-max-frequency = <3500000>;
52                 spi-cpol;
53                 spi-cpha;
54                 reg = <2>;
55         };
56 };
57
58 &qspi {
59         bus-num = <0>;
60         status = "okay";
61
62         qflash0: s25fl128s@0 {
63                 #address-cells = <1>;
64                 #size-cells = <1>;
65                 compatible = "spi-flash";
66                 spi-max-frequency = <20000000>;
67                 reg = <0>;
68         };
69 };
70
71 &duart0 {
72         status = "okay";
73 };
74
75 &duart1 {
76         status = "okay";
77 };
78
79 &lpuart0 {
80         status = "okay";
81 };