2 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4 * Copyright (C) 2016, Freescale Semiconductor
6 * Mingkai Hu <mingkai.hu@nxp.com>
8 * SPDX-License-Identifier: GPL-2.0+ X11
11 /include/ "skeleton64.dtsi"
14 compatible = "fsl,ls1046a";
15 interrupt-parent = <&gic>;
18 compatible = "fixed-clock";
20 clock-frequency = <100000000>;
21 clock-output-names = "sysclk";
24 gic: interrupt-controller@1400000 {
25 compatible = "arm,gic-400";
26 #interrupt-cells = <3>;
28 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
29 <0x0 0x1420000 0 0x10000>, /* GICC */
30 <0x0 0x1440000 0 0x20000>, /* GICH */
31 <0x0 0x1460000 0 0x20000>; /* GICV */
32 interrupts = <1 9 0xf08>;
36 compatible = "simple-bus";
41 clockgen: clocking@1ee1000 {
42 compatible = "fsl,ls1046a-clockgen";
43 reg = <0x0 0x1ee1000 0x0 0x1000>;
49 compatible = "fsl,vf610-dspi";
52 reg = <0x0 0x2100000 0x0 0x10000>;
53 interrupts = <0 64 0x4>;
55 clocks = <&clockgen 4 0>;
62 compatible = "fsl,vf610-dspi";
65 reg = <0x0 0x2110000 0x0 0x10000>;
66 interrupts = <0 65 0x4>;
68 clocks = <&clockgen 4 0>;
75 compatible = "fsl,ifc", "simple-bus";
76 reg = <0x0 0x1530000 0x0 0x10000>;
77 interrupts = <0 43 0x4>;
81 compatible = "fsl,vf610-i2c";
84 reg = <0x0 0x2180000 0x0 0x10000>;
85 interrupts = <0 56 0x4>;
87 clocks = <&clockgen 4 0>;
92 compatible = "fsl,vf610-i2c";
95 reg = <0x0 0x2190000 0x0 0x10000>;
96 interrupts = <0 57 0x4>;
98 clocks = <&clockgen 4 0>;
103 compatible = "fsl,vf610-i2c";
104 #address-cells = <1>;
106 reg = <0x0 0x21a0000 0x0 0x10000>;
107 interrupts = <0 58 0x4>;
109 clocks = <&clockgen 4 0>;
114 compatible = "fsl,vf610-i2c";
115 #address-cells = <1>;
117 reg = <0x0 0x21b0000 0x0 0x10000>;
118 interrupts = <0 59 0x4>;
120 clocks = <&clockgen 4 0>;
124 duart0: serial@21c0500 {
125 compatible = "fsl,ns16550", "ns16550a";
126 reg = <0x00 0x21c0500 0x0 0x100>;
127 interrupts = <0 54 0x4>;
128 clocks = <&clockgen 4 0>;
131 duart1: serial@21c0600 {
132 compatible = "fsl,ns16550", "ns16550a";
133 reg = <0x00 0x21c0600 0x0 0x100>;
134 interrupts = <0 54 0x4>;
135 clocks = <&clockgen 4 0>;
138 duart2: serial@21d0500 {
139 compatible = "fsl,ns16550", "ns16550a";
140 reg = <0x0 0x21d0500 0x0 0x100>;
141 interrupts = <0 55 0x4>;
142 clocks = <&clockgen 4 0>;
145 duart3: serial@21d0600 {
146 compatible = "fsl,ns16550", "ns16550a";
147 reg = <0x0 0x21d0600 0x0 0x100>;
148 interrupts = <0 55 0x4>;
149 clocks = <&clockgen 4 0>;
152 lpuart0: serial@2950000 {
153 compatible = "fsl,ls1021a-lpuart";
154 reg = <0x0 0x2950000 0x0 0x1000>;
155 interrupts = <0 48 0x4>;
156 clocks = <&clockgen 4 0>;
161 lpuart1: serial@2960000 {
162 compatible = "fsl,ls1021a-lpuart";
163 reg = <0x0 0x2960000 0x0 0x1000>;
164 interrupts = <0 49 0x4>;
165 clocks = <&clockgen 4 1>;
170 lpuart2: serial@2970000 {
171 compatible = "fsl,ls1021a-lpuart";
172 reg = <0x0 0x2970000 0x0 0x1000>;
173 interrupts = <0 50 0x4>;
174 clocks = <&clockgen 4 1>;
179 lpuart3: serial@2980000 {
180 compatible = "fsl,ls1021a-lpuart";
181 reg = <0x0 0x2980000 0x0 0x1000>;
182 interrupts = <0 51 0x4>;
183 clocks = <&clockgen 4 1>;
188 lpuart4: serial@2990000 {
189 compatible = "fsl,ls1021a-lpuart";
190 reg = <0x0 0x2990000 0x0 0x1000>;
191 interrupts = <0 52 0x4>;
192 clocks = <&clockgen 4 1>;
197 lpuart5: serial@29a0000 {
198 compatible = "fsl,ls1021a-lpuart";
199 reg = <0x0 0x29a0000 0x0 0x1000>;
200 interrupts = <0 53 0x4>;
201 clocks = <&clockgen 4 1>;
206 qspi: quadspi@1550000 {
207 compatible = "fsl,vf610-qspi";
208 #address-cells = <1>;
210 reg = <0x0 0x1550000 0x0 0x10000>,
211 <0x0 0x40000000 0x0 0x10000000>;
212 reg-names = "QuadSPI", "QuadSPI-memory";
219 compatible = "fsl,layerscape-dwc3";
220 reg = <0x0 0x2f00000 0x0 0x10000>;
221 interrupts = <0 60 4>;
226 compatible = "fsl,layerscape-dwc3";
227 reg = <0x0 0x3000000 0x0 0x10000>;
228 interrupts = <0 61 4>;
233 compatible = "fsl,layerscape-dwc3";
234 reg = <0x0 0x3100000 0x0 0x10000>;
235 interrupts = <0 63 4>;
240 compatible = "fsl,ls-pcie", "snps,dw-pcie";
241 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
242 0x00 0x03480000 0x0 0x40000 /* lut registers */
243 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
244 0x40 0x00000000 0x0 0x20000>; /* configuration space */
245 reg-names = "dbi", "lut", "ctrl", "config";
247 #address-cells = <3>;
250 bus-range = <0x0 0xff>;
251 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
252 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
256 compatible = "fsl,ls-pcie", "snps,dw-pcie";
257 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
258 0x00 0x03580000 0x0 0x40000 /* lut registers */
259 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
260 0x48 0x00000000 0x0 0x20000>; /* configuration space */
261 reg-names = "dbi", "lut", "ctrl", "config";
263 #address-cells = <3>;
267 bus-range = <0x0 0xff>;
268 ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
269 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
273 compatible = "fsl,ls-pcie", "snps,dw-pcie";
274 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
275 0x00 0x03680000 0x0 0x40000 /* lut registers */
276 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
277 0x50 0x00000000 0x0 0x20000>; /* configuration space */
278 reg-names = "dbi", "lut", "ctrl", "config";
280 #address-cells = <3>;
283 bus-range = <0x0 0xff>;
284 ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
285 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */