git.sur5r.net Git - u-boot/blob - arch/arm/dts/fsl-ls2080a.dtsi

   1 /*
   2  * Freescale ls2080a SOC common device tree source
   3  *
   4  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 / {
  10         compatible = "fsl,ls2080a";
  11         interrupt-parent = <&gic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         memory@80000000 {
  16                 device_type = "memory";
  17                 reg = <0x00000000 0x80000000 0 0x80000000>;
  18                       /* DRAM space - 1, size : 2 GB DRAM */
  19         };
  20
  21         gic: interrupt-controller@6000000 {
  22                 compatible = "arm,gic-v3";
  23                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  24                       <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  25                 #interrupt-cells = <3>;
  26                 interrupt-controller;
  27                 interrupts = <1 9 0x4>;
  28         };
  29
  30         timer {
  31                 compatible = "arm,armv8-timer";
  32                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  33                              <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  34                              <1 11 0x8>, /* Virtual PPI, active-low */
  35                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  36         };
  37
  38         serial0: serial@21c0500 {
  39                 device_type = "serial";
  40                 compatible = "fsl,ns16550", "ns16550a";
  41                 reg = <0x0 0x21c0500 0x0 0x100>;
  42                 clock-frequency = <0>;  /* Updated by bootloader */
  43                 interrupts = <0 32 0x1>; /* edge triggered */
  44         };
  45
  46         serial1: serial@21c0600 {
  47                 device_type = "serial";
  48                 compatible = "fsl,ns16550", "ns16550a";
  49                 reg = <0x0 0x21c0600 0x0 0x100>;
  50                 clock-frequency = <0>;  /* Updated by bootloader */
  51                 interrupts = <0 32 0x1>; /* edge triggered */
  52         };
  53
  54         fsl_mc: fsl-mc@80c000000 {
  55                 compatible = "fsl,qoriq-mc";
  56                 reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
  57                       <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
  58         };
  59
  60         dspi: dspi@2100000 {
  61                 compatible = "fsl,vf610-dspi";
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64                 reg = <0x0 0x2100000 0x0 0x10000>;
  65                 interrupts = <0 26 0x4>; /* Level high type */
  66                 num-cs = <6>;
  67         };
  68
  69         qspi: quadspi@1550000 {
  70                 compatible = "fsl,vf610-qspi";
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73                 reg = <0x0 0x20c0000 0x0 0x10000>,
  74                         <0x0 0x20000000 0x0 0x10000000>;
  75                 reg-names = "QuadSPI", "QuadSPI-memory";
  76                 num-cs = <4>;
  77         };
  78
  79         usb0: usb3@3100000 {
  80                 compatible = "fsl,layerscape-dwc3";
  81                 reg = <0x0 0x3100000 0x0 0x10000>;
  82                 interrupts = <0 80 0x4>; /* Level high type */
  83                 dr_mode = "host";
  84         };
  85
  86         usb1: usb3@3110000 {
  87                 compatible = "fsl,layerscape-dwc3";
  88                 reg = <0x0 0x3110000 0x0 0x10000>;
  89                 interrupts = <0 81 0x4>; /* Level high type */
  90                 dr_mode = "host";
  91         };
  92
  93         pcie@3400000 {
  94                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
  95                 reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
  96                        0x00 0x03480000 0x0 0x80000   /* lut registers */
  97                        0x10 0x00000000 0x0 0x20000>; /* configuration space */
  98                 reg-names = "dbi", "lut", "config";
  99                 #address-cells = <3>;
 100                 #size-cells = <2>;
 101                 device_type = "pci";
 102                 num-lanes = <4>;
 103                 bus-range = <0x0 0xff>;
 104                 ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000   /* downstream I/O */
 105                           0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 106         };
 107
 108         pcie@3500000 {
 109                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 110                 reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 111                        0x00 0x03580000 0x0 0x80000   /* lut registers */
 112                        0x12 0x00000000 0x0 0x20000>; /* configuration space */
 113                 reg-names = "dbi", "lut", "config";
 114                 #address-cells = <3>;
 115                 #size-cells = <2>;
 116                 device_type = "pci";
 117                 num-lanes = <4>;
 118                 bus-range = <0x0 0xff>;
 119                 ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000   /* downstream I/O */
 120                           0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 121         };
 122
 123         pcie@3600000 {
 124                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 125                 reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 126                        0x00 0x03680000 0x0 0x80000   /* lut registers */
 127                        0x14 0x00000000 0x0 0x20000>; /* configuration space */
 128                 reg-names = "dbi", "lut", "config";
 129                 #address-cells = <3>;
 130                 #size-cells = <2>;
 131                 device_type = "pci";
 132                 num-lanes = <8>;
 133                 bus-range = <0x0 0xff>;
 134                 ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000   /* downstream I/O */
 135                           0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 136         };
 137
 138         pcie@3700000 {
 139                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 140                 reg = <0x00 0x03700000 0x0 0x80000   /* dbi registers */
 141                        0x00 0x03780000 0x0 0x80000   /* lut registers */
 142                        0x16 0x00000000 0x0 0x20000>; /* configuration space */
 143                 reg-names = "dbi", "lut", "config";
 144                 #address-cells = <3>;
 145                 #size-cells = <2>;
 146                 device_type = "pci";
 147                 num-lanes = <4>;
 148                 bus-range = <0x0 0xff>;
 149                 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000   /* downstream I/O */
 150                           0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 151         };
 152 };