git.sur5r.net Git - u-boot/blob - arch/arm/dts/imx53.dtsi

   1 /*
   2  * Copyright 2016 Beckhoff Automation
   3  * Copyright 2011 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include "skeleton.dtsi"
  15 #include "imx53-pinfunc.h"
  16 #include <dt-bindings/clock/imx5-clock.h>
  17 #include <dt-bindings/gpio/gpio.h>
  18 #include <dt-bindings/input/input.h>
  19 #include <dt-bindings/interrupt-controller/irq.h>
  20
  21 / {
  22         aliases {
  23                 serial1 = &uart2;
  24         };
  25
  26         soc {
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29                 compatible = "simple-bus";
  30                 ranges;
  31
  32                 aips@50000000 { /* AIPS1 */
  33                         compatible = "fsl,aips-bus", "simple-bus";
  34                         #address-cells = <1>;
  35                         #size-cells = <1>;
  36                         reg = <0x50000000 0x10000000>;
  37                         ranges;
  38
  39                         iomuxc: iomuxc@53fa8000 {
  40                                 compatible = "fsl,imx53-iomuxc";
  41                                 reg = <0x53fa8000 0x4000>;
  42                         };
  43
  44                         gpr: iomuxc-gpr@53fa8000 {
  45                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
  46                                 reg = <0x53fa8000 0xc>;
  47                         };
  48
  49                         uart2: serial@53fc0000 {
  50                                 compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
  51                                 reg = <0x53fc0000 0x4000>;
  52                                 interrupts = <32>;
  53                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
  54                                          <&clks IMX5_CLK_UART2_PER_GATE>;
  55                                 clock-names = "ipg", "per";
  56                                 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
  57                                 dma-names = "rx", "tx";
  58                                 status = "disabled";
  59                         };
  60
  61                         clks: ccm@53fd4000{
  62                                 compatible = "fsl,imx53-ccm";
  63                                 reg = <0x53fd4000 0x4000>;
  64                                 interrupts = <0 71 0x04 0 72 0x04>;
  65                                 #clock-cells = <1>;
  66                         };
  67
  68                         gpio7: gpio@53fe4000 {
  69                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
  70                                 reg = <0x53fe4000 0x4000>;
  71                                 interrupts = <107 108>;
  72                                 gpio-controller;
  73                                 #gpio-cells = <2>;
  74                                 interrupt-controller;
  75                                 #interrupt-cells = <2>;
  76                         };
  77                 };
  78
  79                 aips@60000000 { /* AIPS2 */
  80                         compatible = "fsl,aips-bus", "simple-bus";
  81                         #address-cells = <1>;
  82                         #size-cells = <1>;
  83                         reg = <0x60000000 0x10000000>;
  84                         ranges;
  85
  86                         sdma: sdma@63fb0000 {
  87                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
  88                                 reg = <0x63fb0000 0x4000>;
  89                                 interrupts = <6>;
  90                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
  91                                          <&clks IMX5_CLK_SDMA_GATE>;
  92                                 clock-names = "ipg", "ahb";
  93                                 #dma-cells = <3>;
  94                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
  95                         };
  96
  97
  98                         fec: ethernet@63fec000 {
  99                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 100                                 reg = <0x63fec000 0x4000>;
 101                                 interrupts = <87>;
 102                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 103                                          <&clks IMX5_CLK_FEC_GATE>,
 104                                          <&clks IMX5_CLK_FEC_GATE>;
 105                                 clock-names = "ipg", "ahb", "ptp";
 106                                 status = "disabled";
 107                         };
 108                 };
 109         };
 110 };