2 * Copyright 2016 Beckhoff Automation
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
15 #include "imx53-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/input/input.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
36 tzic: tz-interrupt-controller@fffc000 {
37 compatible = "fsl,imx53-tzic", "fsl,tzic";
39 #interrupt-cells = <1>;
40 reg = <0x0fffc000 0x4000>;
46 compatible = "simple-bus";
47 interrupt-parent = <&tzic>;
50 aips@50000000 { /* AIPS1 */
51 compatible = "fsl,aips-bus", "simple-bus";
54 reg = <0x50000000 0x10000000>;
57 iomuxc: iomuxc@53fa8000 {
58 compatible = "fsl,imx53-iomuxc";
59 reg = <0x53fa8000 0x4000>;
62 gpr: iomuxc-gpr@53fa8000 {
63 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
64 reg = <0x53fa8000 0xc>;
67 uart2: serial@53fc0000 {
68 compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
69 reg = <0x53fc0000 0x4000>;
71 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
72 <&clks IMX5_CLK_UART2_PER_GATE>;
73 clock-names = "ipg", "per";
74 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
75 dma-names = "rx", "tx";
80 compatible = "fsl,imx53-ccm";
81 reg = <0x53fd4000 0x4000>;
82 interrupts = <0 71 0x04 0 72 0x04>;
86 gpio1: gpio@53f84000 {
87 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
88 reg = <0x53f84000 0x4000>;
93 #interrupt-cells = <2>;
96 gpio2: gpio@53f88000 {
97 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
98 reg = <0x53f88000 0x4000>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
106 gpio3: gpio@53f8c000 {
107 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
108 reg = <0x53f8c000 0x4000>;
109 interrupts = <54 55>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
116 gpio4: gpio@53f90000 {
117 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
118 reg = <0x53f90000 0x4000>;
119 interrupts = <56 57>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
126 gpio5: gpio@53fdc000 {
127 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
128 reg = <0x53fdc000 0x4000>;
129 interrupts = <103 104>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
136 gpio6: gpio@53fe0000 {
137 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
138 reg = <0x53fe0000 0x4000>;
139 interrupts = <105 106>;
142 interrupt-controller;
143 #interrupt-cells = <2>;
146 gpio7: gpio@53fe4000 {
147 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
148 reg = <0x53fe4000 0x4000>;
149 interrupts = <107 108>;
152 interrupt-controller;
153 #interrupt-cells = <2>;
157 #address-cells = <1>;
159 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
160 reg = <0x53fec000 0x4000>;
162 clocks = <&clks IMX5_CLK_I2C3_GATE>;
167 aips@60000000 { /* AIPS2 */
168 compatible = "fsl,aips-bus", "simple-bus";
169 #address-cells = <1>;
171 reg = <0x60000000 0x10000000>;
174 sdma: sdma@63fb0000 {
175 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
176 reg = <0x63fb0000 0x4000>;
178 clocks = <&clks IMX5_CLK_SDMA_GATE>,
179 <&clks IMX5_CLK_SDMA_GATE>;
180 clock-names = "ipg", "ahb";
182 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
185 fec: ethernet@63fec000 {
186 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
187 reg = <0x63fec000 0x4000>;
189 clocks = <&clks IMX5_CLK_FEC_GATE>,
190 <&clks IMX5_CLK_FEC_GATE>,
191 <&clks IMX5_CLK_FEC_GATE>;
192 clock-names = "ipg", "ahb", "ptp";
197 #address-cells = <1>;
199 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
200 reg = <0x63fc4000 0x4000>;
202 clocks = <&clks IMX5_CLK_I2C2_GATE>;
207 #address-cells = <1>;
209 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
210 reg = <0x63fc8000 0x4000>;
212 clocks = <&clks IMX5_CLK_I2C1_GATE>;