git.sur5r.net Git - u-boot/blob - arch/arm/dts/imx6dl-mamoj.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2018 BTicino
   4  * Copyright (C) 2018 Amarula Solutions B.V.
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include "imx6dl.dtsi"
  11
  12 / {
  13         model = "BTicino i.MX6DL Mamoj board";
  14         compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
  15 };
  16
  17 &fec {
  18         pinctrl-names = "default";
  19         pinctrl-0 = <&pinctrl_enet>;
  20         phy-mode = "mii";
  21         status = "okay";
  22 };
  23
  24 &uart3 {
  25         pinctrl-names = "default";
  26         pinctrl-0 = <&pinctrl_uart3>;
  27         status = "okay";
  28 };
  29
  30 &usdhc3 {
  31         pinctrl-names = "default";
  32         pinctrl-0 = <&pinctrl_usdhc3>;
  33         bus-width = <8>;
  34         non-removable;
  35         keep-power-in-suspend;
  36         status = "okay";
  37 };
  38
  39 &iomuxc {
  40         pinctrl_enet: enetgrp {
  41                 fsl,pins = <
  42                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
  43                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
  44                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b1
  45                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
  46                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
  47                         MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2      0x1b0b0
  48                         MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3      0x1b0b0
  49                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
  50                         MX6QDL_PAD_GPIO_19__ENET_TX_ER          0x1b0b0
  51                         MX6QDL_PAD_GPIO_18__ENET_RX_CLK         0x1b0b1
  52                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
  53                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
  54                         MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2      0x1b0b0
  55                         MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3      0x1b0b0
  56                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
  57                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
  58                         MX6QDL_PAD_KEY_COL3__ENET_CRS           0x1b0b0
  59                         MX6QDL_PAD_KEY_ROW1__ENET_COL           0x1b0b0
  60                 >;
  61         };
  62
  63         pinctrl_uart3: uart3grp {
  64                 fsl,pins = <
  65                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
  66                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
  67                 >;
  68         };
  69
  70         pinctrl_usdhc3: usdhc3grp {
  71                 fsl,pins = <
  72                         MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
  73                         MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
  74                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
  75                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
  76                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
  77                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
  78                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x17059
  79                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x17059
  80                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x17059
  81                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x17059
  82                 >;
  83         };
  84 };