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rockchip: dts: tinker: add usb host power supply node
[u-boot] / arch / arm / dts / imx6sll-evk.dts
1 /*
2  * Copyright (C) 2016 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8
9 /dts-v1/;
10
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include "imx6sll.dtsi"
14
15 / {
16         model = "Freescale i.MX6SLL EVK Board";
17         compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
18
19         memory {
20                 reg = <0x80000000 0x80000000>;
21         };
22
23         backlight {
24                 compatible = "pwm-backlight";
25                 pwms = <&pwm1 0 5000000>;
26                 brightness-levels = <0 4 8 16 32 64 128 255>;
27                 default-brightness-level = <6>;
28                 status = "okay";
29         };
30
31         battery: max8903@0 {
32                 compatible = "fsl,max8903-charger";
33                 pinctrl-names = "default";
34                 dok_input = <&gpio4 13 1>;
35                 uok_input = <&gpio4 13 1>;
36                 chg_input = <&gpio4 15 1>;
37                 flt_input = <&gpio4 14 1>;
38                 fsl,dcm_always_high;
39                 fsl,dc_valid;
40                 fsl,adc_disable;
41                 status = "okay";
42         };
43
44         pxp_v4l2_out {
45                 compatible = "fsl,imx6sl-pxp-v4l2";
46                 status = "okay";
47         };
48
49         regulators {
50                 compatible = "simple-bus";
51                 #address-cells = <1>;
52                 #size-cells = <0>;
53
54                 reg_usb_otg1_vbus: regulator@0 {
55                         compatible = "regulator-fixed";
56                         reg = <0>;
57                         regulator-name = "usb_otg1_vbus";
58                         regulator-min-microvolt = <5000000>;
59                         regulator-max-microvolt = <5000000>;
60                         gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
61                         enable-active-high;
62                 };
63
64                 reg_usb_otg2_vbus: regulator@1 {
65                         compatible = "regulator-fixed";
66                         reg = <1>;
67                         regulator-name = "usb_otg2_vbus";
68                         regulator-min-microvolt = <5000000>;
69                         regulator-max-microvolt = <5000000>;
70                         gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
71                         enable-active-high;
72                 };
73
74                 reg_aud3v: regulator@2 {
75                         compatible = "regulator-fixed";
76                         reg = <2>;
77                         regulator-name = "wm8962-supply-3v15";
78                         regulator-min-microvolt = <3150000>;
79                         regulator-max-microvolt = <3150000>;
80                         regulator-boot-on;
81                 };
82
83                 reg_aud4v: regulator@3 {
84                         compatible = "regulator-fixed";
85                         reg = <3>;
86                         regulator-name = "wm8962-supply-4v2";
87                         regulator-min-microvolt = <4325000>;
88                         regulator-max-microvolt = <4325000>;
89                         regulator-boot-on;
90                 };
91
92                 reg_lcd: regulator@4 {
93                         compatible = "regulator-fixed";
94                         reg = <4>;
95                         regulator-name = "lcd-pwr";
96                         gpio = <&gpio4 8 0>;
97                         enable-active-high;
98                 };
99
100                 reg_sd1_vmmc: sd1_vmmc {
101                         compatible = "regulator-fixed";
102                         regulator-name = "SD1_SPWR";
103                         regulator-min-microvolt = <3000000>;
104                         regulator-max-microvolt = <3000000>;
105                         gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
106                         enable-active-high;
107                 };
108
109                 reg_sd2_vmmc: sd2_vmmc {
110                         compatible = "regulator-fixed";
111                         regulator-name = "eMMC-VCCQ";
112                         regulator-min-microvolt = <1800000>;
113                         regulator-max-microvolt = <1800000>;
114                         regulator-boot-on;
115                 };
116
117                 reg_sd3_vmmc: sd3_vmmc {
118                         compatible = "regulator-fixed";
119                         regulator-name = "SD3_WIFI";
120                         regulator-min-microvolt = <3000000>;
121                         regulator-max-microvolt = <3000000>;
122                         gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
123                         enable-active-high;
124                 };
125
126         };
127
128         sound {
129                 compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
130                 model = "wm8962-audio";
131                 cpu-dai = <&ssi2>;
132                 audio-codec = <&codec>;
133                 audio-routing =
134                         "Headphone Jack", "HPOUTL",
135                         "Headphone Jack", "HPOUTR",
136                         "Ext Spk", "SPKOUTL",
137                         "Ext Spk", "SPKOUTR",
138                         "AMIC", "MICBIAS",
139                         "IN3R", "AMIC";
140                 mux-int-port = <2>;
141                 mux-ext-port = <3>;
142                 codec-master;
143                 hp-det-gpios = <&gpio4 24 1>;
144         };
145 };
146
147 &audmux {
148         pinctrl-names = "default";
149         pinctrl-0 = <&pinctrl_audmux3>;
150         status = "okay";
151 };
152
153 &clks {
154         assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
155         assigned-clock-rates = <393216000>;
156 };
157
158 &cpu0 {
159         arm-supply = <&sw1a_reg>;
160         soc-supply = <&sw1c_reg>;
161 };
162
163 &i2c1 {
164         clock-frequency = <100000>;
165         pinctrl-names = "default";
166         pinctrl-0 = <&pinctrl_i2c1>;
167         status = "okay";
168
169         pmic: pfuze100@08 {
170                 compatible = "fsl,pfuze100";
171                 reg = <0x08>;
172
173                 regulators {
174                         sw1a_reg: sw1ab {
175                                 regulator-min-microvolt = <300000>;
176                                 regulator-max-microvolt = <1875000>;
177                                 regulator-boot-on;
178                                 regulator-always-on;
179                                 regulator-ramp-delay = <6250>;
180                         };
181
182                         sw1c_reg: sw1c {
183                                 regulator-min-microvolt = <300000>;
184                                 regulator-max-microvolt = <1875000>;
185                                 regulator-boot-on;
186                                 regulator-always-on;
187                                 regulator-ramp-delay = <6250>;
188                         };
189
190                         sw2_reg: sw2 {
191                                 regulator-min-microvolt = <800000>;
192                                 regulator-max-microvolt = <3300000>;
193                                 regulator-boot-on;
194                                 regulator-always-on;
195                         };
196
197                         sw3a_reg: sw3a {
198                                 regulator-min-microvolt = <400000>;
199                                 regulator-max-microvolt = <1975000>;
200                                 regulator-boot-on;
201                                 regulator-always-on;
202                         };
203
204                         sw3b_reg: sw3b {
205                                 regulator-min-microvolt = <400000>;
206                                 regulator-max-microvolt = <1975000>;
207                                 regulator-boot-on;
208                                 regulator-always-on;
209                         };
210
211                         sw4_reg: sw4 {
212                                 regulator-min-microvolt = <800000>;
213                                 regulator-max-microvolt = <3300000>;
214                         };
215
216                         swbst_reg: swbst {
217                                 regulator-min-microvolt = <5000000>;
218                                 regulator-max-microvolt = <5150000>;
219                         };
220
221                         snvs_reg: vsnvs {
222                                 regulator-min-microvolt = <1000000>;
223                                 regulator-max-microvolt = <3000000>;
224                                 regulator-boot-on;
225                                 regulator-always-on;
226                         };
227
228                         vref_reg: vrefddr {
229                                 regulator-boot-on;
230                                 regulator-always-on;
231                         };
232
233                         vgen1_reg: vgen1 {
234                                 regulator-min-microvolt = <800000>;
235                                 regulator-max-microvolt = <1550000>;
236                                 regulator-always-on;
237                         };
238
239                         vgen2_reg: vgen2 {
240                                 regulator-min-microvolt = <800000>;
241                                 regulator-max-microvolt = <1550000>;
242                         };
243
244                         vgen3_reg: vgen3 {
245                                 regulator-min-microvolt = <1800000>;
246                                 regulator-max-microvolt = <3300000>;
247                         };
248
249                         vgen4_reg: vgen4 {
250                                 regulator-min-microvolt = <1800000>;
251                                 regulator-max-microvolt = <3300000>;
252                                 regulator-always-on;
253                         };
254
255                         vgen5_reg: vgen5 {
256                                 regulator-min-microvolt = <1800000>;
257                                 regulator-max-microvolt = <3300000>;
258                                 regulator-always-on;
259                         };
260
261                         vgen6_reg: vgen6 {
262                                 regulator-min-microvolt = <1800000>;
263                                 regulator-max-microvolt = <3300000>;
264                                 regulator-always-on;
265                         };
266                 };
267         };
268
269         max17135: max17135@48 {
270                 pinctrl-names = "default";
271                 pinctrl-0 = <&pinctrl_max17135>;
272                 compatible = "maxim,max17135";
273                 reg = <0x48>;
274                 status = "okay";
275
276                 vneg_pwrup = <1>;
277                 gvee_pwrup = <2>;
278                 vpos_pwrup = <10>;
279                 gvdd_pwrup = <12>;
280                 gvdd_pwrdn = <1>;
281                 vpos_pwrdn = <2>;
282                 gvee_pwrdn = <8>;
283                 vneg_pwrdn = <10>;
284                 gpio_pmic_pwrgood = <&gpio2 13 0>;
285                 gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
286                 gpio_pmic_wakeup = <&gpio2 14 0>;
287                 gpio_pmic_v3p3 = <&gpio2 7 0>;
288                 gpio_pmic_intr = <&gpio2 12 0>;
289
290                 regulators {
291                         DISPLAY_reg: DISPLAY {
292                                 regulator-name = "DISPLAY";
293                         };
294
295                         GVDD_reg: GVDD {
296                                 /* 20v */
297                                 regulator-name = "GVDD";
298                         };
299
300                         GVEE_reg: GVEE {
301                                 /* -22v */
302                                 regulator-name = "GVEE";
303                         };
304
305                         HVINN_reg: HVINN {
306                                 /* -22v */
307                                 regulator-name = "HVINN";
308                         };
309
310                         HVINP_reg: HVINP {
311                                 /* 20v */
312                                 regulator-name = "HVINP";
313                         };
314
315                         VCOM_reg: VCOM {
316                                 regulator-name = "VCOM";
317                                 /* 2's-compliment, -4325000 */
318                                 regulator-min-microvolt = <0xffbe0178>;
319                                 /* 2's-compliment, -500000 */
320                                 regulator-max-microvolt = <0xfff85ee0>;
321                         };
322
323                         VNEG_reg: VNEG {
324                                 /* -15v */
325                                 regulator-name = "VNEG";
326                         };
327
328                         VPOS_reg: VPOS {
329                                 /* 15v */
330                                 regulator-name = "VPOS";
331                         };
332
333                         V3P3_reg: V3P3 {
334                                 regulator-name = "V3P3";
335                         };
336                 };
337         };
338 };
339
340 &i2c3 {
341         clock-frequency = <100000>;
342         pinctrl-names = "default";
343         pinctrl-0 = <&pinctrl_i2c3>;
344         status = "okay";
345
346         codec: wm8962@1a {
347                 compatible = "wlf,wm8962";
348                 reg = <0x1a>;
349                 clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
350                 DCVDD-supply = <&vgen3_reg>;
351                 DBVDD-supply = <&reg_aud3v>;
352                 AVDD-supply = <&vgen3_reg>;
353                 CPVDD-supply = <&vgen3_reg>;
354                 MICVDD-supply = <&reg_aud3v>;
355                 PLLVDD-supply = <&vgen3_reg>;
356                 SPKVDD1-supply = <&reg_aud4v>;
357                 SPKVDD2-supply = <&reg_aud4v>;
358                 amic-mono;
359         };
360 };
361
362 &gpc {
363         fsl,ldo-bypass = <1>;
364 };
365
366 &iomuxc {
367         pinctrl-names = "default";
368         pinctrl-0 = <&pinctrl_hog>;
369
370         imx6sll-evk {
371                 pinctrl_hog: hoggrp {
372                         fsl,pins = <
373                                 MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
374                                 MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059
375                                 MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
376                                 /*
377                                  * Must set the LVE of pad SD2_RESET, otherwise current
378                                  * leakage through eMMC chip will pull high the VCCQ to
379                                  * 2.6v, which will impact SD1 and SD3 SD3.0 voltage switch.
380                                  */
381                                 MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059
382                                 MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
383                                 MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */
384                                 MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */
385                                 MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
386                                 MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
387                                 /* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */
388                                 MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
389                                 MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
390                                 MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15  0x17000
391                         >;
392                 };
393
394                 pinctrl_audmux3: audmux3grp {
395                         fsl,pins = <
396                                 MX6SLL_PAD_AUD_TXC__AUD3_TXC            0x4130b0
397                                 MX6SLL_PAD_AUD_TXFS__AUD3_TXFS          0x4130b0
398                                 MX6SLL_PAD_AUD_TXD__AUD3_TXD            0x4110b0
399                                 MX6SLL_PAD_AUD_RXD__AUD3_RXD            0x4130b0
400                                 MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT      0x4130b0
401                         >;
402                 };
403
404                 pinctrl_csi1: csi1grp {
405                         fsl,pins = <
406                                 MX6SLL_PAD_EPDC_GDRL__CSI_MCLK          0x1b088
407                                 MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK       0x1b088
408                                 MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC         0x1b088
409                                 MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC         0x1b088
410                                 MX6SLL_PAD_EPDC_DATA02__CSI_DATA02      0x1b088
411                                 MX6SLL_PAD_EPDC_DATA03__CSI_DATA03      0x1b088
412                                 MX6SLL_PAD_EPDC_DATA04__CSI_DATA04      0x1b088
413                                 MX6SLL_PAD_EPDC_DATA05__CSI_DATA05      0x1b088
414                                 MX6SLL_PAD_EPDC_DATA06__CSI_DATA06      0x1b088
415                                 MX6SLL_PAD_EPDC_DATA07__CSI_DATA07      0x1b088
416                                 MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08       0x1b088
417                                 MX6SLL_PAD_EPDC_SDLE__CSI_DATA09        0x1b088
418                                 MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26       0x80000000
419                                 MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25        0x80000000
420                         >;
421                 };
422
423                 pinctrl_epdc0: epdcgrp0 {
424                         fsl,pins = <
425                                 MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00     0x100b1
426                                 MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01     0x100b1
427                                 MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02     0x100b1
428                                 MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03     0x100b1
429                                 MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04     0x100b1
430                                 MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05     0x100b1
431                                 MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06     0x100b1
432                                 MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07     0x100b1
433                                 MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08     0x100b1
434                                 MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09     0x100b1
435                                 MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10     0x100b1
436                                 MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11     0x100b1
437                                 MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12     0x100b1
438                                 MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13     0x100b1
439                                 MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14     0x100b1
440                                 MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15     0x100b1
441                                 MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P     0x100b1
442                                 MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE         0x100b1
443                                 MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE         0x100b1
444                                 MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR       0x100b1
445                                 MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0       0x100b1
446                                 MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK       0x100b1
447                                 MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE         0x100b1
448                                 MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL         0x100b1
449                                 MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP         0x100b1
450                        >;
451                 };
452
453                 pinctrl_lcdif_dat: lcdifdatgrp {
454                         fsl,pins = <
455                                 MX6SLL_PAD_LCD_DATA00__LCD_DATA00       0x79
456                                 MX6SLL_PAD_LCD_DATA01__LCD_DATA01       0x79
457                                 MX6SLL_PAD_LCD_DATA02__LCD_DATA02       0x79
458                                 MX6SLL_PAD_LCD_DATA03__LCD_DATA03       0x79
459                                 MX6SLL_PAD_LCD_DATA04__LCD_DATA04       0x79
460                                 MX6SLL_PAD_LCD_DATA05__LCD_DATA05       0x79
461                                 MX6SLL_PAD_LCD_DATA06__LCD_DATA06       0x79
462                                 MX6SLL_PAD_LCD_DATA07__LCD_DATA07       0x79
463                                 MX6SLL_PAD_LCD_DATA08__LCD_DATA08       0x79
464                                 MX6SLL_PAD_LCD_DATA09__LCD_DATA09       0x79
465                                 MX6SLL_PAD_LCD_DATA10__LCD_DATA10       0x79
466                                 MX6SLL_PAD_LCD_DATA11__LCD_DATA11       0x79
467                                 MX6SLL_PAD_LCD_DATA12__LCD_DATA12       0x79
468                                 MX6SLL_PAD_LCD_DATA13__LCD_DATA13       0x79
469                                 MX6SLL_PAD_LCD_DATA14__LCD_DATA14       0x79
470                                 MX6SLL_PAD_LCD_DATA15__LCD_DATA15       0x79
471                                 MX6SLL_PAD_LCD_DATA16__LCD_DATA16       0x79
472                                 MX6SLL_PAD_LCD_DATA17__LCD_DATA17       0x79
473                                 MX6SLL_PAD_LCD_DATA18__LCD_DATA18       0x79
474                                 MX6SLL_PAD_LCD_DATA19__LCD_DATA19       0x79
475                                 MX6SLL_PAD_LCD_DATA20__LCD_DATA20       0x79
476                                 MX6SLL_PAD_LCD_DATA21__LCD_DATA21       0x79
477                                 MX6SLL_PAD_LCD_DATA22__LCD_DATA22       0x79
478                                 MX6SLL_PAD_LCD_DATA23__LCD_DATA23       0x79
479                         >;
480                 };
481
482                 pinctrl_lcdif_ctrl: lcdifctrlgrp {
483                         fsl,pins = <
484                                 MX6SLL_PAD_LCD_CLK__LCD_CLK             0x79
485                                 MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE       0x79
486                                 MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC         0x79
487                                 MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC         0x79
488                                 MX6SLL_PAD_LCD_RESET__LCD_RESET         0x79
489                                 MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08      0x79
490                         >;
491                 };
492
493                 pinctrl_max17135: max17135grp-1 {
494                         fsl,pins = <
495                                 MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13    0x80000000  /* pwrgood */
496                                 MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03       0x80000000  /* vcom_ctrl */
497                                 MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14    0x80000000  /* wakeup */
498                                 MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07   0x80000000  /* v3p3 */
499                                 MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12     0x80000000  /* pwr int */
500                         >;
501                 };
502
503                 pinctrl_spdif: spdifgrp {
504                         fsl,pins = <
505                                 MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x4130b0
506                         >;
507                 };
508
509                 pinctrl_uart1: uart1grp {
510                         fsl,pins = <
511                                 MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
512                                 MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
513                         >;
514                 };
515
516                 pinctrl_uart5: uart5grp {
517                         fsl,pins = <
518                                 MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1  /* bt reg on */
519                                 MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1
520                                 MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1
521                                 MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1
522                                 MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1
523                         >;
524                 };
525
526                 pinctrl_uart5dte: uart5dtegrp {
527                         fsl,pins = <
528                                 MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1
529                                 MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1
530                                 MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1
531                                 MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1
532                         >;
533                 };
534
535                 pinctrl_usdhc1: usdhc1grp {
536                         fsl,pins = <
537                                 MX6SLL_PAD_SD1_CMD__SD1_CMD     0x17059
538                                 MX6SLL_PAD_SD1_CLK__SD1_CLK     0x13059
539                                 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
540                                 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
541                                 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
542                                 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
543                         >;
544                 };
545
546                 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
547                         fsl,pins = <
548                                 MX6SLL_PAD_SD1_CMD__SD1_CMD     0x170b9
549                                 MX6SLL_PAD_SD1_CLK__SD1_CLK     0x130b9
550                                 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
551                                 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
552                                 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
553                                 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
554                         >;
555                 };
556
557                 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
558                         fsl,pins = <
559                                 MX6SLL_PAD_SD1_CMD__SD1_CMD     0x170f9
560                                 MX6SLL_PAD_SD1_CLK__SD1_CLK     0x130f9
561                                 MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
562                                 MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
563                                 MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
564                                 MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
565                         >;
566                 };
567
568                 pinctrl_usdhc2: usdhc2grp {
569                         fsl,pins = <
570                                 MX6SLL_PAD_SD2_CMD__SD2_CMD             0x17059
571                                 MX6SLL_PAD_SD2_CLK__SD2_CLK             0x13059
572                                 MX6SLL_PAD_SD2_DATA0__SD2_DATA0         0x17059
573                                 MX6SLL_PAD_SD2_DATA1__SD2_DATA1         0x17059
574                                 MX6SLL_PAD_SD2_DATA2__SD2_DATA2         0x17059
575                                 MX6SLL_PAD_SD2_DATA3__SD2_DATA3         0x17059
576                                 MX6SLL_PAD_SD2_DATA4__SD2_DATA4         0x17059
577                                 MX6SLL_PAD_SD2_DATA5__SD2_DATA5         0x17059
578                                 MX6SLL_PAD_SD2_DATA6__SD2_DATA6         0x17059
579                                 MX6SLL_PAD_SD2_DATA7__SD2_DATA7         0x17059
580                                 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE       0x413059
581                         >;
582                 };
583
584                 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
585                         fsl,pins = <
586                                 MX6SLL_PAD_SD2_CMD__SD2_CMD             0x170b9
587                                 MX6SLL_PAD_SD2_CLK__SD2_CLK             0x130b9
588                                 MX6SLL_PAD_SD2_DATA0__SD2_DATA0         0x170b9
589                                 MX6SLL_PAD_SD2_DATA1__SD2_DATA1         0x170b9
590                                 MX6SLL_PAD_SD2_DATA2__SD2_DATA2         0x170b9
591                                 MX6SLL_PAD_SD2_DATA3__SD2_DATA3         0x170b9
592                                 MX6SLL_PAD_SD2_DATA4__SD2_DATA4         0x170b9
593                                 MX6SLL_PAD_SD2_DATA5__SD2_DATA5         0x170b9
594                                 MX6SLL_PAD_SD2_DATA6__SD2_DATA6         0x170b9
595                                 MX6SLL_PAD_SD2_DATA7__SD2_DATA7         0x170b9
596                                 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE       0x4130b9
597                         >;
598                 };
599
600                 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
601                         fsl,pins = <
602                                 MX6SLL_PAD_SD2_CMD__SD2_CMD             0x170f9
603                                 MX6SLL_PAD_SD2_CLK__SD2_CLK             0x130f9
604                                 MX6SLL_PAD_SD2_DATA0__SD2_DATA0         0x170f9
605                                 MX6SLL_PAD_SD2_DATA1__SD2_DATA1         0x170f9
606                                 MX6SLL_PAD_SD2_DATA2__SD2_DATA2         0x170f9
607                                 MX6SLL_PAD_SD2_DATA3__SD2_DATA3         0x170f9
608                                 MX6SLL_PAD_SD2_DATA4__SD2_DATA4         0x170f9
609                                 MX6SLL_PAD_SD2_DATA5__SD2_DATA5         0x170f9
610                                 MX6SLL_PAD_SD2_DATA6__SD2_DATA6         0x170f9
611                                 MX6SLL_PAD_SD2_DATA7__SD2_DATA7         0x170f9
612                                 MX6SLL_PAD_GPIO4_IO21__SD2_STROBE       0x4130f9
613                         >;
614                 };
615
616                 pinctrl_usdhc3: usdhc3grp {
617                         fsl,pins = <
618                                 MX6SLL_PAD_SD3_CMD__SD3_CMD     0x17059
619                                 MX6SLL_PAD_SD3_CLK__SD3_CLK     0x13059
620                                 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059
621                                 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059
622                                 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059
623                                 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059
624                         >;
625                 };
626
627                 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
628                         fsl,pins = <
629                                 MX6SLL_PAD_SD3_CMD__SD3_CMD     0x170b9
630                                 MX6SLL_PAD_SD3_CLK__SD3_CLK     0x130b9
631                                 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
632                                 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
633                                 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
634                                 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
635                         >;
636                 };
637
638                 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
639                         fsl,pins = <
640                                 MX6SLL_PAD_SD3_CMD__SD3_CMD     0x170f9
641                                 MX6SLL_PAD_SD3_CLK__SD3_CLK     0x130f9
642                                 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
643                                 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
644                                 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
645                                 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
646                         >;
647                 };
648
649                 pinctrl_usbotg1: usbotg1grp {
650                         fsl,pins = <
651                                 MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
652                         >;
653                 };
654
655                 pinctrl_i2c1: i2c1grp {
656                         fsl,pins = <
657                                 MX6SLL_PAD_I2C1_SCL__I2C1_SCL    0x4001b8b1
658                                 MX6SLL_PAD_I2C1_SDA__I2C1_SDA    0x4001b8b1
659                         >;
660                 };
661
662                 pinctrl_i2c3: i2c3grp {
663                         fsl,pins = <
664                                 MX6SLL_PAD_AUD_RXFS__I2C3_SCL  0x4041b8b1
665                                 MX6SLL_PAD_AUD_RXC__I2C3_SDA   0x4041b8b1
666                         >;
667                 };
668
669                 pinctrl_pwm1: pmw1grp {
670                         fsl,pins = <
671                                 MX6SLL_PAD_PWM1__PWM1_OUT   0x110b0
672                         >;
673                 };
674         };
675 };
676
677 &lcdif {
678         pinctrl-names = "default";
679         pinctrl-0 = <&pinctrl_lcdif_dat
680                      &pinctrl_lcdif_ctrl>;
681         lcd-supply = <&reg_lcd>;
682         display = <&display>;
683         status = "okay";
684
685         display: display {
686                 bits-per-pixel = <16>;
687                 bus-width = <24>;
688
689                 display-timings {
690                         native-mode = <&timing0>;
691                         timing0: timing0 {
692                                 clock-frequency = <33500000>;
693                                 hactive = <800>;
694                                 vactive = <480>;
695                                 hback-porch = <89>;
696                                 hfront-porch = <164>;
697                                 vback-porch = <23>;
698                                 vfront-porch = <10>;
699                                 hsync-len = <10>;
700                                 vsync-len = <10>;
701                                 hsync-active = <0>;
702                                 vsync-active = <0>;
703                                 de-active = <1>;
704                                 pixelclk-active = <0>;
705                         };
706                 };
707         };
708 };
709
710 &pxp {
711         status = "okay";
712 };
713
714 &pwm1 {
715         pinctrl-names = "default";
716         pinctrl-0 = <&pinctrl_pwm1>;
717         status = "okay";
718 };
719
720 &uart1 {
721         pinctrl-names = "default";
722         pinctrl-0 = <&pinctrl_uart1>;
723         status = "okay";
724 };
725
726 &uart5 {
727         pinctrl-names = "default";
728         pinctrl-0 = <&pinctrl_uart5>;
729         fsl,uart-has-rtscts;
730         /* for DTE mode, add below change */
731         /* fsl,dte-mode; */
732         /* pinctrl-0 = <&pinctrl_uart5dte>; */
733         status = "disabled";
734 };
735
736 &usdhc1 {
737         pinctrl-names = "default", "state_100mhz", "state_200mhz";
738         pinctrl-0 = <&pinctrl_usdhc1>;
739         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
740         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
741         cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
742         wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
743         keep-power-in-suspend;
744         enable-sdio-wakeup;
745         vmmc-supply = <&reg_sd1_vmmc>;
746         status = "okay";
747 };
748
749 &usdhc2 {
750         pinctrl-names = "default", "state_100mhz", "state_200mhz";
751         pinctrl-0 = <&pinctrl_usdhc2>;
752         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
753         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
754         vqmmc-supply = <&reg_sd2_vmmc>;
755         bus-width = <8>;
756         no-removable;
757         status = "okay";
758 };
759
760 &usdhc3 {
761         pinctrl-names = "default", "state_100mhz", "state_200mhz";
762         pinctrl-0 = <&pinctrl_usdhc3>;
763         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
764         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
765         cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
766         keep-power-in-suspend;
767         enable-sdio-wakeup;
768         vmmc-supply = <&reg_sd3_vmmc>;
769         status = "okay";
770 };
771
772 &usbotg1 {
773         vbus-supply = <&reg_usb_otg1_vbus>;
774         pinctrl-names = "default";
775         pinctrl-0 = <&pinctrl_usbotg1>;
776         disable-over-current;
777         srp-disable;
778         hnp-disable;
779         adp-disable;
780         status = "okay";
781 };
782
783 &usbotg2 {
784         vbus-supply = <&reg_usb_otg2_vbus>;
785         dr_mode = "host";
786         disable-over-current;
787         status = "okay";
788 };
789
790 &epdc {
791         pinctrl-names = "default";
792         pinctrl-0 = <&pinctrl_epdc0>;
793         V3P3-supply = <&V3P3_reg>;
794         VCOM-supply = <&VCOM_reg>;
795         DISPLAY-supply = <&DISPLAY_reg>;
796         status = "okay";
797 };
798
799 &ssi2 {
800         status = "okay";
801 };