2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/clock/imx6ul-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6ul-pinfunc.h"
14 #include "skeleton.dtsi"
57 compatible = "arm,cortex-a7";
60 clock-latency = <61036>; /* two CLK32 periods */
67 fsl,soc-operating-points = <
73 clocks = <&clks IMX6UL_CLK_ARM>,
74 <&clks IMX6UL_CLK_PLL2_BUS>,
75 <&clks IMX6UL_CLK_PLL2_PFD2>,
76 <&clks IMX6UL_CA7_SECONDARY_SEL>,
77 <&clks IMX6UL_CLK_STEP>,
78 <&clks IMX6UL_CLK_PLL1_SW>,
79 <&clks IMX6UL_CLK_PLL1_SYS>,
80 <&clks IMX6UL_PLL1_BYPASS>,
81 <&clks IMX6UL_CLK_PLL1>,
82 <&clks IMX6UL_PLL1_BYPASS_SRC>,
83 <&clks IMX6UL_CLK_OSC>;
84 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
85 "secondary_sel", "step", "pll1_sw",
86 "pll1_sys", "pll1_bypass", "pll1",
87 "pll1_bypass_src", "osc";
88 arm-supply = <®_arm>;
89 soc-supply = <®_soc>;
93 intc: interrupt-controller@00a01000 {
94 compatible = "arm,cortex-a7-gic";
95 #interrupt-cells = <3>;
97 reg = <0x00a01000 0x1000>,
104 compatible = "fixed-clock";
106 clock-frequency = <32768>;
107 clock-output-names = "ckil";
111 compatible = "fixed-clock";
113 clock-frequency = <24000000>;
114 clock-output-names = "osc";
118 compatible = "fixed-clock";
120 clock-frequency = <0>;
121 clock-output-names = "ipp_di0";
125 compatible = "fixed-clock";
127 clock-frequency = <0>;
128 clock-output-names = "ipp_di1";
132 #address-cells = <1>;
134 compatible = "simple-bus";
135 interrupt-parent = <&gpc>;
139 compatible = "arm,cortex-a7-pmu";
140 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
144 ocram: sram@00900000 {
145 compatible = "mmio-sram";
146 reg = <0x00900000 0x20000>;
149 dma_apbh: dma-apbh@01804000 {
150 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
151 reg = <0x01804000 0x2000>;
152 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
153 <0 13 IRQ_TYPE_LEVEL_HIGH>,
154 <0 13 IRQ_TYPE_LEVEL_HIGH>,
155 <0 13 IRQ_TYPE_LEVEL_HIGH>;
156 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
159 clocks = <&clks IMX6UL_CLK_APBHDMA>;
162 gpmi: gpmi-nand@01806000 {
163 compatible = "fsl,imx6q-gpmi-nand";
164 #address-cells = <1>;
166 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
167 reg-names = "gpmi-nand", "bch";
168 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
169 interrupt-names = "bch";
170 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
171 <&clks IMX6UL_CLK_GPMI_APB>,
172 <&clks IMX6UL_CLK_GPMI_BCH>,
173 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
174 <&clks IMX6UL_CLK_PER_BCH>;
175 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
176 "gpmi_bch_apb", "per1_bch";
177 dmas = <&dma_apbh 0>;
182 aips1: aips-bus@02000000 {
183 compatible = "fsl,aips-bus", "simple-bus";
184 #address-cells = <1>;
186 reg = <0x02000000 0x100000>;
190 compatible = "fsl,spba-bus", "simple-bus";
191 #address-cells = <1>;
193 reg = <0x02000000 0x40000>;
196 ecspi1: ecspi@02008000 {
197 #address-cells = <1>;
199 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
200 reg = <0x02008000 0x4000>;
201 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&clks IMX6UL_CLK_ECSPI1>,
203 <&clks IMX6UL_CLK_ECSPI1>;
204 clock-names = "ipg", "per";
208 ecspi2: ecspi@0200c000 {
209 #address-cells = <1>;
211 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
212 reg = <0x0200c000 0x4000>;
213 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&clks IMX6UL_CLK_ECSPI2>,
215 <&clks IMX6UL_CLK_ECSPI2>;
216 clock-names = "ipg", "per";
220 ecspi3: ecspi@02010000 {
221 #address-cells = <1>;
223 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
224 reg = <0x02010000 0x4000>;
225 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clks IMX6UL_CLK_ECSPI3>,
227 <&clks IMX6UL_CLK_ECSPI3>;
228 clock-names = "ipg", "per";
232 ecspi4: ecspi@02014000 {
233 #address-cells = <1>;
235 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
236 reg = <0x02014000 0x4000>;
237 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clks IMX6UL_CLK_ECSPI4>,
239 <&clks IMX6UL_CLK_ECSPI4>;
240 clock-names = "ipg", "per";
244 uart7: serial@02018000 {
245 compatible = "fsl,imx6ul-uart",
247 reg = <0x02018000 0x4000>;
248 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
250 <&clks IMX6UL_CLK_UART7_SERIAL>;
251 clock-names = "ipg", "per";
255 uart1: serial@02020000 {
256 compatible = "fsl,imx6ul-uart",
258 reg = <0x02020000 0x4000>;
259 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
261 <&clks IMX6UL_CLK_UART1_SERIAL>;
262 clock-names = "ipg", "per";
266 uart8: serial@02024000 {
267 compatible = "fsl,imx6ul-uart",
269 reg = <0x02024000 0x4000>;
270 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
272 <&clks IMX6UL_CLK_UART8_SERIAL>;
273 clock-names = "ipg", "per";
278 #sound-dai-cells = <0>;
279 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
280 reg = <0x02028000 0x4000>;
281 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
283 <&clks IMX6UL_CLK_SAI1>,
284 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
285 clock-names = "bus", "mclk1", "mclk2", "mclk3";
286 dmas = <&sdma 35 24 0>,
288 dma-names = "rx", "tx";
293 #sound-dai-cells = <0>;
294 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
295 reg = <0x0202c000 0x4000>;
296 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
298 <&clks IMX6UL_CLK_SAI2>,
299 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
300 clock-names = "bus", "mclk1", "mclk2", "mclk3";
301 dmas = <&sdma 37 24 0>,
303 dma-names = "rx", "tx";
308 #sound-dai-cells = <0>;
309 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
310 reg = <0x02030000 0x4000>;
311 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
313 <&clks IMX6UL_CLK_SAI3>,
314 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
315 clock-names = "bus", "mclk1", "mclk2", "mclk3";
316 dmas = <&sdma 39 24 0>,
318 dma-names = "rx", "tx";
324 compatible = "fsl,imx6ul-tsc";
325 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
326 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clks IMX6UL_CLK_IPG>,
329 <&clks IMX6UL_CLK_ADC2>;
330 clock-names = "tsc", "adc";
335 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
336 reg = <0x02080000 0x4000>;
337 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&clks IMX6UL_CLK_PWM1>,
339 <&clks IMX6UL_CLK_PWM1>;
340 clock-names = "ipg", "per";
346 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
347 reg = <0x02084000 0x4000>;
348 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clks IMX6UL_CLK_PWM2>,
350 <&clks IMX6UL_CLK_PWM2>;
351 clock-names = "ipg", "per";
357 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
358 reg = <0x02088000 0x4000>;
359 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clks IMX6UL_CLK_PWM3>,
361 <&clks IMX6UL_CLK_PWM3>;
362 clock-names = "ipg", "per";
368 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
369 reg = <0x0208c000 0x4000>;
370 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clks IMX6UL_CLK_PWM4>,
372 <&clks IMX6UL_CLK_PWM4>;
373 clock-names = "ipg", "per";
378 can1: flexcan@02090000 {
379 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
380 reg = <0x02090000 0x4000>;
381 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
383 <&clks IMX6UL_CLK_CAN1_SERIAL>;
384 clock-names = "ipg", "per";
388 can2: flexcan@02094000 {
389 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
390 reg = <0x02094000 0x4000>;
391 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
393 <&clks IMX6UL_CLK_CAN2_SERIAL>;
394 clock-names = "ipg", "per";
399 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
400 reg = <0x02098000 0x4000>;
401 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
403 <&clks IMX6UL_CLK_GPT1_SERIAL>;
404 clock-names = "ipg", "per";
407 gpio1: gpio@0209c000 {
408 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
409 reg = <0x0209c000 0x4000>;
410 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
414 interrupt-controller;
415 #interrupt-cells = <2>;
416 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
420 gpio2: gpio@020a0000 {
421 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
422 reg = <0x020a0000 0x4000>;
423 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-controller;
428 #interrupt-cells = <2>;
429 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
432 gpio3: gpio@020a4000 {
433 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
434 reg = <0x020a4000 0x4000>;
435 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 gpio-ranges = <&iomuxc 0 65 29>;
444 gpio4: gpio@020a8000 {
445 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
446 reg = <0x020a8000 0x4000>;
447 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
451 interrupt-controller;
452 #interrupt-cells = <2>;
453 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
456 gpio5: gpio@020ac000 {
457 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
458 reg = <0x020ac000 0x4000>;
459 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
463 interrupt-controller;
464 #interrupt-cells = <2>;
465 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
468 fec2: ethernet@020b4000 {
469 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
470 reg = <0x020b4000 0x4000>;
471 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&clks IMX6UL_CLK_ENET>,
474 <&clks IMX6UL_CLK_ENET_AHB>,
475 <&clks IMX6UL_CLK_ENET_PTP>,
476 <&clks IMX6UL_CLK_ENET2_REF_125M>,
477 <&clks IMX6UL_CLK_ENET2_REF_125M>;
478 clock-names = "ipg", "ahb", "ptp",
479 "enet_clk_ref", "enet_out";
480 fsl,num-tx-queues=<1>;
481 fsl,num-rx-queues=<1>;
486 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
487 reg = <0x020b8000 0x4000>;
488 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&clks IMX6UL_CLK_KPP>;
493 wdog1: wdog@020bc000 {
494 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
495 reg = <0x020bc000 0x4000>;
496 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&clks IMX6UL_CLK_WDOG1>;
500 wdog2: wdog@020c0000 {
501 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
502 reg = <0x020c0000 0x4000>;
503 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&clks IMX6UL_CLK_WDOG2>;
509 compatible = "fsl,imx6ul-ccm";
510 reg = <0x020c4000 0x4000>;
511 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
515 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
518 anatop: anatop@020c8000 {
519 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
520 "syscon", "simple-bus";
521 reg = <0x020c8000 0x1000>;
522 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
526 reg_3p0: regulator-3p0 {
527 compatible = "fsl,anatop-regulator";
528 regulator-name = "vdd3p0";
529 regulator-min-microvolt = <2625000>;
530 regulator-max-microvolt = <3400000>;
531 anatop-reg-offset = <0x120>;
532 anatop-vol-bit-shift = <8>;
533 anatop-vol-bit-width = <5>;
534 anatop-min-bit-val = <0>;
535 anatop-min-voltage = <2625000>;
536 anatop-max-voltage = <3400000>;
537 anatop-enable-bit = <0>;
540 reg_arm: regulator-vddcore {
541 compatible = "fsl,anatop-regulator";
542 regulator-name = "cpu";
543 regulator-min-microvolt = <725000>;
544 regulator-max-microvolt = <1450000>;
546 anatop-reg-offset = <0x140>;
547 anatop-vol-bit-shift = <0>;
548 anatop-vol-bit-width = <5>;
549 anatop-delay-reg-offset = <0x170>;
550 anatop-delay-bit-shift = <24>;
551 anatop-delay-bit-width = <2>;
552 anatop-min-bit-val = <1>;
553 anatop-min-voltage = <725000>;
554 anatop-max-voltage = <1450000>;
557 reg_soc: regulator-vddsoc {
558 compatible = "fsl,anatop-regulator";
559 regulator-name = "vddsoc";
560 regulator-min-microvolt = <725000>;
561 regulator-max-microvolt = <1450000>;
563 anatop-reg-offset = <0x140>;
564 anatop-vol-bit-shift = <18>;
565 anatop-vol-bit-width = <5>;
566 anatop-delay-reg-offset = <0x170>;
567 anatop-delay-bit-shift = <28>;
568 anatop-delay-bit-width = <2>;
569 anatop-min-bit-val = <1>;
570 anatop-min-voltage = <725000>;
571 anatop-max-voltage = <1450000>;
575 usbphy1: usbphy@020c9000 {
576 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
577 reg = <0x020c9000 0x1000>;
578 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&clks IMX6UL_CLK_USBPHY1>;
580 phy-3p0-supply = <®_3p0>;
581 fsl,anatop = <&anatop>;
584 usbphy2: usbphy@020ca000 {
585 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
586 reg = <0x020ca000 0x1000>;
587 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&clks IMX6UL_CLK_USBPHY2>;
589 phy-3p0-supply = <®_3p0>;
590 fsl,anatop = <&anatop>;
593 snvs: snvs@020cc000 {
594 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
595 reg = <0x020cc000 0x4000>;
597 snvs_rtc: snvs-rtc-lp {
598 compatible = "fsl,sec-v4.0-mon-rtc-lp";
601 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
605 snvs_poweroff: snvs-poweroff {
606 compatible = "syscon-poweroff";
613 snvs_pwrkey: snvs-powerkey {
614 compatible = "fsl,sec-v4.0-pwrkey";
616 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
617 linux,keycode = <KEY_POWER>;
622 epit1: epit@020d0000 {
623 reg = <0x020d0000 0x4000>;
624 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
627 epit2: epit@020d4000 {
628 reg = <0x020d4000 0x4000>;
629 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
633 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
634 reg = <0x020d8000 0x4000>;
635 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
641 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
642 reg = <0x020dc000 0x4000>;
643 interrupt-controller;
644 #interrupt-cells = <3>;
645 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
646 interrupt-parent = <&intc>;
649 iomuxc: iomuxc@020e0000 {
650 compatible = "fsl,imx6ul-iomuxc";
651 reg = <0x020e0000 0x4000>;
654 gpr: iomuxc-gpr@020e4000 {
655 compatible = "fsl,imx6ul-iomuxc-gpr",
656 "fsl,imx6q-iomuxc-gpr", "syscon";
657 reg = <0x020e4000 0x4000>;
661 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
662 reg = <0x020e8000 0x4000>;
663 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
665 <&clks IMX6UL_CLK_GPT2_SERIAL>;
666 clock-names = "ipg", "per";
669 sdma: sdma@020ec000 {
670 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
672 reg = <0x020ec000 0x4000>;
673 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&clks IMX6UL_CLK_SDMA>,
675 <&clks IMX6UL_CLK_SDMA>;
676 clock-names = "ipg", "ahb";
678 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
682 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
683 reg = <0x020f0000 0x4000>;
684 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&clks IMX6UL_CLK_PWM5>,
686 <&clks IMX6UL_CLK_PWM5>;
687 clock-names = "ipg", "per";
693 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
694 reg = <0x020f4000 0x4000>;
695 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&clks IMX6UL_CLK_PWM6>,
697 <&clks IMX6UL_CLK_PWM6>;
698 clock-names = "ipg", "per";
704 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
705 reg = <0x020f8000 0x4000>;
706 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&clks IMX6UL_CLK_PWM7>,
708 <&clks IMX6UL_CLK_PWM7>;
709 clock-names = "ipg", "per";
715 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
716 reg = <0x020fc000 0x4000>;
717 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clks IMX6UL_CLK_PWM8>,
719 <&clks IMX6UL_CLK_PWM8>;
720 clock-names = "ipg", "per";
726 aips2: aips-bus@02100000 {
727 compatible = "fsl,aips-bus", "simple-bus";
728 #address-cells = <1>;
730 reg = <0x02100000 0x100000>;
733 usbotg1: usb@02184000 {
734 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
735 reg = <0x02184000 0x200>;
736 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&clks IMX6UL_CLK_USBOH3>;
738 fsl,usbphy = <&usbphy1>;
739 fsl,usbmisc = <&usbmisc 0>;
740 fsl,anatop = <&anatop>;
741 ahb-burst-config = <0x0>;
742 tx-burst-size-dword = <0x10>;
743 rx-burst-size-dword = <0x10>;
747 usbotg2: usb@02184200 {
748 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
749 reg = <0x02184200 0x200>;
750 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&clks IMX6UL_CLK_USBOH3>;
752 fsl,usbphy = <&usbphy2>;
753 fsl,usbmisc = <&usbmisc 1>;
754 ahb-burst-config = <0x0>;
755 tx-burst-size-dword = <0x10>;
756 rx-burst-size-dword = <0x10>;
760 usbmisc: usbmisc@02184800 {
762 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
763 reg = <0x02184800 0x200>;
766 fec1: ethernet@02188000 {
767 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
768 reg = <0x02188000 0x4000>;
769 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&clks IMX6UL_CLK_ENET>,
772 <&clks IMX6UL_CLK_ENET_AHB>,
773 <&clks IMX6UL_CLK_ENET_PTP>,
774 <&clks IMX6UL_CLK_ENET_REF>,
775 <&clks IMX6UL_CLK_ENET_REF>;
776 clock-names = "ipg", "ahb", "ptp",
777 "enet_clk_ref", "enet_out";
778 fsl,num-tx-queues=<1>;
779 fsl,num-rx-queues=<1>;
783 usdhc1: usdhc@02190000 {
784 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
785 reg = <0x02190000 0x4000>;
786 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clks IMX6UL_CLK_USDHC1>,
788 <&clks IMX6UL_CLK_USDHC1>,
789 <&clks IMX6UL_CLK_USDHC1>;
790 clock-names = "ipg", "ahb", "per";
795 usdhc2: usdhc@02194000 {
796 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
797 reg = <0x02194000 0x4000>;
798 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&clks IMX6UL_CLK_USDHC2>,
800 <&clks IMX6UL_CLK_USDHC2>,
801 <&clks IMX6UL_CLK_USDHC2>;
802 clock-names = "ipg", "ahb", "per";
808 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
809 reg = <0x02198000 0x4000>;
810 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clks IMX6UL_CLK_ADC1>;
814 fsl,adck-max-frequency = <30000000>, <40000000>,
820 #address-cells = <1>;
822 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
823 reg = <0x021a0000 0x4000>;
824 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&clks IMX6UL_CLK_I2C1>;
830 #address-cells = <1>;
832 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
833 reg = <0x021a4000 0x4000>;
834 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clks IMX6UL_CLK_I2C2>;
840 #address-cells = <1>;
842 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
843 reg = <0x021a8000 0x4000>;
844 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&clks IMX6UL_CLK_I2C3>;
849 mmdc: mmdc@021b0000 {
850 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
851 reg = <0x021b0000 0x4000>;
854 lcdif: lcdif@021c8000 {
855 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
856 reg = <0x021c8000 0x4000>;
857 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
859 <&clks IMX6UL_CLK_LCDIF_APB>,
860 <&clks IMX6UL_CLK_DUMMY>;
861 clock-names = "pix", "axi", "disp_axi";
865 qspi: qspi@021e0000 {
866 #address-cells = <1>;
868 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
869 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
870 reg-names = "QuadSPI", "QuadSPI-memory";
871 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&clks IMX6UL_CLK_QSPI>,
873 <&clks IMX6UL_CLK_QSPI>;
874 clock-names = "qspi_en", "qspi";
878 uart2: serial@021e8000 {
879 compatible = "fsl,imx6ul-uart",
881 reg = <0x021e8000 0x4000>;
882 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
884 <&clks IMX6UL_CLK_UART2_SERIAL>;
885 clock-names = "ipg", "per";
889 uart3: serial@021ec000 {
890 compatible = "fsl,imx6ul-uart",
892 reg = <0x021ec000 0x4000>;
893 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
895 <&clks IMX6UL_CLK_UART3_SERIAL>;
896 clock-names = "ipg", "per";
900 uart4: serial@021f0000 {
901 compatible = "fsl,imx6ul-uart",
903 reg = <0x021f0000 0x4000>;
904 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
906 <&clks IMX6UL_CLK_UART4_SERIAL>;
907 clock-names = "ipg", "per";
911 uart5: serial@021f4000 {
912 compatible = "fsl,imx6ul-uart",
914 reg = <0x021f4000 0x4000>;
915 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
917 <&clks IMX6UL_CLK_UART5_SERIAL>;
918 clock-names = "ipg", "per";
923 #address-cells = <1>;
925 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
926 reg = <0x021f8000 0x4000>;
927 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&clks IMX6UL_CLK_I2C4>;
932 uart6: serial@021fc000 {
933 compatible = "fsl,imx6ul-uart",
935 reg = <0x021fc000 0x4000>;
936 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
938 <&clks IMX6UL_CLK_UART6_SERIAL>;
939 clock-names = "ipg", "per";