git.sur5r.net Git - u-boot/blob - arch/arm/dts/ls1021a-qds.dts

   1 /*
   2  * Freescale ls1021a QDS board device tree source
   3  *
   4  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /dts-v1/;
  10 #include "ls1021a.dtsi"
  11
  12 / {
  13         model = "LS1021A QDS Board";
  14
  15         aliases {
  16                 enet0_rgmii_phy = &rgmii_phy1;
  17                 enet1_rgmii_phy = &rgmii_phy2;
  18                 enet2_rgmii_phy = &rgmii_phy3;
  19                 enet0_sgmii_phy = &sgmii_phy1c;
  20                 enet1_sgmii_phy = &sgmii_phy1d;
  21                 spi1 = &dspi0;
  22         };
  23 };
  24
  25 &dspi0 {
  26         bus-num = <0>;
  27         status = "okay";
  28
  29         dspiflash: at45db021d@0 {
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 compatible = "spi-flash";
  33                 spi-max-frequency = <16000000>;
  34                 spi-cpol;
  35                 spi-cpha;
  36                 reg = <0>;
  37         };
  38 };
  39
  40 &i2c0 {
  41         status = "okay";
  42
  43         pca9547: mux@77 {
  44                 reg = <0x77>;
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 i2c@0 {
  49                         #address-cells = <1>;
  50                         #size-cells = <0>;
  51                         reg = <0x0>;
  52
  53                         ds3232: rtc@68 {
  54                                 compatible = "dallas,ds3232";
  55                                 reg = <0x68>;
  56                                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
  57                         };
  58                 };
  59
  60                 i2c@2 {
  61                         #address-cells = <1>;
  62                         #size-cells = <0>;
  63                         reg = <0x2>;
  64
  65                         ina220@40 {
  66                                 compatible = "ti,ina220";
  67                                 reg = <0x40>;
  68                                 shunt-resistor = <1000>;
  69                         };
  70
  71                         ina220@41 {
  72                                 compatible = "ti,ina220";
  73                                 reg = <0x41>;
  74                                 shunt-resistor = <1000>;
  75                         };
  76                 };
  77
  78                 i2c@3 {
  79                         #address-cells = <1>;
  80                         #size-cells = <0>;
  81                         reg = <0x3>;
  82
  83                         eeprom@56 {
  84                                 compatible = "atmel,24c512";
  85                                 reg = <0x56>;
  86                         };
  87
  88                         eeprom@57 {
  89                                 compatible = "atmel,24c512";
  90                                 reg = <0x57>;
  91                         };
  92
  93                         adt7461a@4c {
  94                                 compatible = "adi,adt7461a";
  95                                 reg = <0x4c>;
  96                         };
  97                 };
  98         };
  99 };
 100
 101 &ifc {
 102         #address-cells = <2>;
 103         #size-cells = <1>;
 104         /* NOR, NAND Flashes and FPGA on board */
 105         ranges = <0x0 0x0 0x60000000 0x08000000
 106                   0x2 0x0 0x7e800000 0x00010000
 107                   0x3 0x0 0x7fb00000 0x00000100>;
 108         status = "okay";
 109
 110         nor@0,0 {
 111                 #address-cells = <1>;
 112                 #size-cells = <1>;
 113                 compatible = "cfi-flash";
 114                 reg = <0x0 0x0 0x8000000>;
 115                 bank-width = <2>;
 116                 device-width = <1>;
 117         };
 118
 119         fpga: board-control@3,0 {
 120                 #address-cells = <1>;
 121                 #size-cells = <1>;
 122                 compatible = "simple-bus";
 123                 reg = <0x3 0x0 0x0000100>;
 124                 bank-width = <1>;
 125                 device-width = <1>;
 126                 ranges = <0 3 0 0x100>;
 127
 128                 mdio-mux-emi1 {
 129                         compatible = "mdio-mux-mmioreg";
 130                         mdio-parent-bus = <&mdio0>;
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         reg = <0x54 1>; /* BRDCFG4 */
 134                         mux-mask = <0xe0>; /* EMI1[2:0] */
 135
 136                         /* Onboard PHYs */
 137                         ls1021amdio0: mdio@0 {
 138                                 reg = <0>;
 139                                 #address-cells = <1>;
 140                                 #size-cells = <0>;
 141                                 rgmii_phy1: ethernet-phy@1 {
 142                                         reg = <0x1>;
 143                                 };
 144                         };
 145
 146                         ls1021amdio1: mdio@20 {
 147                                 reg = <0x20>;
 148                                 #address-cells = <1>;
 149                                 #size-cells = <0>;
 150                                 rgmii_phy2: ethernet-phy@2 {
 151                                         reg = <0x2>;
 152                                 };
 153                         };
 154
 155                         ls1021amdio2: mdio@40 {
 156                                 reg = <0x40>;
 157                                 #address-cells = <1>;
 158                                 #size-cells = <0>;
 159                                 rgmii_phy3: ethernet-phy@3 {
 160                                         reg = <0x3>;
 161                                 };
 162                         };
 163
 164                         ls1021amdio3: mdio@60 {
 165                                 reg = <0x60>;
 166                                 #address-cells = <1>;
 167                                 #size-cells = <0>;
 168                                 sgmii_phy1c: ethernet-phy@1c {
 169                                         reg = <0x1c>;
 170                                 };
 171                         };
 172
 173                         ls1021amdio4: mdio@80 {
 174                                 reg = <0x80>;
 175                                 #address-cells = <1>;
 176                                 #size-cells = <0>;
 177                                 sgmii_phy1d: ethernet-phy@1d {
 178                                         reg = <0x1d>;
 179                                 };
 180                         };
 181                 };
 182         };
 183 };
 184
 185 &lpuart0 {
 186         status = "okay";
 187 };
 188
 189 &mdio0 {
 190         tbi0: tbi-phy@8 {
 191                 reg = <0x8>;
 192                 device_type = "tbi-phy";
 193         };
 194 };
 195
 196 &uart0 {
 197         status = "okay";
 198 };
 199
 200 &uart1 {
 201         status = "okay";
 202 };