git.sur5r.net Git - u-boot/blob - arch/arm/dts/ls1021a-qds.dts

   1 /*
   2  * Freescale ls1021a QDS board device tree source
   3  *
   4  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /dts-v1/;
  10 #include "ls1021a.dtsi"
  11
  12 / {
  13         model = "LS1021A QDS Board";
  14
  15         aliases {
  16                 enet0_rgmii_phy = &rgmii_phy1;
  17                 enet1_rgmii_phy = &rgmii_phy2;
  18                 enet2_rgmii_phy = &rgmii_phy3;
  19                 enet0_sgmii_phy = &sgmii_phy1c;
  20                 enet1_sgmii_phy = &sgmii_phy1d;
  21         };
  22 };
  23
  24 &dspi0 {
  25         bus-num = <0>;
  26         status = "okay";
  27
  28         dspiflash: at45db021d@0 {
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31                 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
  32                 spi-max-frequency = <16000000>;
  33                 spi-cpol;
  34                 spi-cpha;
  35                 reg = <0>;
  36         };
  37 };
  38
  39 &i2c0 {
  40         status = "okay";
  41
  42         pca9547: mux@77 {
  43                 reg = <0x77>;
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 i2c@0 {
  48                         #address-cells = <1>;
  49                         #size-cells = <0>;
  50                         reg = <0x0>;
  51
  52                         ds3232: rtc@68 {
  53                                 compatible = "dallas,ds3232";
  54                                 reg = <0x68>;
  55                                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
  56                         };
  57                 };
  58
  59                 i2c@2 {
  60                         #address-cells = <1>;
  61                         #size-cells = <0>;
  62                         reg = <0x2>;
  63
  64                         ina220@40 {
  65                                 compatible = "ti,ina220";
  66                                 reg = <0x40>;
  67                                 shunt-resistor = <1000>;
  68                         };
  69
  70                         ina220@41 {
  71                                 compatible = "ti,ina220";
  72                                 reg = <0x41>;
  73                                 shunt-resistor = <1000>;
  74                         };
  75                 };
  76
  77                 i2c@3 {
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                         reg = <0x3>;
  81
  82                         eeprom@56 {
  83                                 compatible = "atmel,24c512";
  84                                 reg = <0x56>;
  85                         };
  86
  87                         eeprom@57 {
  88                                 compatible = "atmel,24c512";
  89                                 reg = <0x57>;
  90                         };
  91
  92                         adt7461a@4c {
  93                                 compatible = "adi,adt7461a";
  94                                 reg = <0x4c>;
  95                         };
  96                 };
  97         };
  98 };
  99
 100 &ifc {
 101         #address-cells = <2>;
 102         #size-cells = <1>;
 103         /* NOR, NAND Flashes and FPGA on board */
 104         ranges = <0x0 0x0 0x60000000 0x08000000
 105                   0x2 0x0 0x7e800000 0x00010000
 106                   0x3 0x0 0x7fb00000 0x00000100>;
 107         status = "okay";
 108
 109         nor@0,0 {
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 compatible = "cfi-flash";
 113                 reg = <0x0 0x0 0x8000000>;
 114                 bank-width = <2>;
 115                 device-width = <1>;
 116         };
 117
 118         fpga: board-control@3,0 {
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 compatible = "simple-bus";
 122                 reg = <0x3 0x0 0x0000100>;
 123                 bank-width = <1>;
 124                 device-width = <1>;
 125                 ranges = <0 3 0 0x100>;
 126
 127                 mdio-mux-emi1 {
 128                         compatible = "mdio-mux-mmioreg";
 129                         mdio-parent-bus = <&mdio0>;
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                         reg = <0x54 1>; /* BRDCFG4 */
 133                         mux-mask = <0xe0>; /* EMI1[2:0] */
 134
 135                         /* Onboard PHYs */
 136                         ls1021amdio0: mdio@0 {
 137                                 reg = <0>;
 138                                 #address-cells = <1>;
 139                                 #size-cells = <0>;
 140                                 rgmii_phy1: ethernet-phy@1 {
 141                                         reg = <0x1>;
 142                                 };
 143                         };
 144
 145                         ls1021amdio1: mdio@20 {
 146                                 reg = <0x20>;
 147                                 #address-cells = <1>;
 148                                 #size-cells = <0>;
 149                                 rgmii_phy2: ethernet-phy@2 {
 150                                         reg = <0x2>;
 151                                 };
 152                         };
 153
 154                         ls1021amdio2: mdio@40 {
 155                                 reg = <0x40>;
 156                                 #address-cells = <1>;
 157                                 #size-cells = <0>;
 158                                 rgmii_phy3: ethernet-phy@3 {
 159                                         reg = <0x3>;
 160                                 };
 161                         };
 162
 163                         ls1021amdio3: mdio@60 {
 164                                 reg = <0x60>;
 165                                 #address-cells = <1>;
 166                                 #size-cells = <0>;
 167                                 sgmii_phy1c: ethernet-phy@1c {
 168                                         reg = <0x1c>;
 169                                 };
 170                         };
 171
 172                         ls1021amdio4: mdio@80 {
 173                                 reg = <0x80>;
 174                                 #address-cells = <1>;
 175                                 #size-cells = <0>;
 176                                 sgmii_phy1d: ethernet-phy@1d {
 177                                         reg = <0x1d>;
 178                                 };
 179                         };
 180                 };
 181         };
 182 };
 183
 184 &lpuart0 {
 185         status = "okay";
 186 };
 187
 188 &mdio0 {
 189         tbi0: tbi-phy@8 {
 190                 reg = <0x8>;
 191                 device_type = "tbi-phy";
 192         };
 193 };
 194
 195 &uart0 {
 196         status = "okay";
 197 };
 198
 199 &uart1 {
 200         status = "okay";
 201 };