2 * Freescale ls1021a SOC common device tree source
4 * Copyright 2013-2015 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
9 #include "skeleton.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "fsl,ls1021a";
14 interrupt-parent = <&gic>;
31 compatible = "arm,cortex-a7";
34 clocks = <&cluster1_clk>;
38 compatible = "arm,cortex-a7";
41 clocks = <&cluster1_clk>;
46 compatible = "arm,armv7-timer";
47 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
54 compatible = "arm,cortex-a7-pmu";
55 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
60 compatible = "simple-bus";
64 interrupt-parent = <&gic>;
67 gic: interrupt-controller@1400000 {
68 compatible = "arm,cortex-a7-gic";
69 #interrupt-cells = <3>;
71 reg = <0x1401000 0x1000>,
75 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
80 compatible = "fsl,ifc", "simple-bus";
81 reg = <0x1530000 0x10000>;
82 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
86 compatible = "fsl,ls1021a-dcfg", "syscon";
87 reg = <0x1ee0000 0x10000>;
91 esdhc: esdhc@1560000 {
92 compatible = "fsl,esdhc";
93 reg = <0x1560000 0x10000>;
94 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
95 clock-frequency = <0>;
96 voltage-ranges = <1800 1800 3300 3300>;
104 compatible = "fsl,ls1021a-scfg", "syscon";
105 reg = <0x1570000 0x10000>;
109 clockgen: clocking@1ee1000 {
110 #address-cells = <1>;
112 ranges = <0x0 0x1ee1000 0x10000>;
115 compatible = "fixed-clock";
117 clock-output-names = "sysclk";
121 compatible = "fsl,qoriq-core-pll-2.0";
125 clock-output-names = "cga-pll1", "cga-pll1-div2",
129 platform_clk: pll@c00 {
130 compatible = "fsl,qoriq-core-pll-2.0";
134 clock-output-names = "platform-clk", "platform-clk-div2";
137 cluster1_clk: clk0c0@0 {
138 compatible = "fsl,qoriq-core-mux-2.0";
141 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
142 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
143 clock-output-names = "cluster1-clk";
147 dspi0: dspi@2100000 {
148 compatible = "fsl,vf610-dspi";
149 #address-cells = <1>;
151 reg = <0x2100000 0x10000>;
152 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
153 clock-names = "dspi";
154 clocks = <&platform_clk 1>;
160 dspi1: dspi@2110000 {
161 compatible = "fsl,vf610-dspi";
162 #address-cells = <1>;
164 reg = <0x2110000 0x10000>;
165 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
166 clock-names = "dspi";
167 clocks = <&platform_clk 1>;
174 compatible = "fsl,vf610-i2c";
175 #address-cells = <1>;
177 reg = <0x2180000 0x10000>;
178 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&platform_clk 1>;
185 compatible = "fsl,vf610-i2c";
186 #address-cells = <1>;
188 reg = <0x2190000 0x10000>;
189 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&platform_clk 1>;
196 compatible = "fsl,vf610-i2c";
197 #address-cells = <1>;
199 reg = <0x21a0000 0x10000>;
200 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&platform_clk 1>;
206 uart0: serial@21c0500 {
207 compatible = "fsl,16550-FIFO64", "ns16550a";
208 reg = <0x21c0500 0x100>;
209 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
210 clock-frequency = <0>;
215 uart1: serial@21c0600 {
216 compatible = "fsl,16550-FIFO64", "ns16550a";
217 reg = <0x21c0600 0x100>;
218 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
219 clock-frequency = <0>;
224 uart2: serial@21d0500 {
225 compatible = "fsl,16550-FIFO64", "ns16550a";
226 reg = <0x21d0500 0x100>;
227 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
228 clock-frequency = <0>;
233 uart3: serial@21d0600 {
234 compatible = "fsl,16550-FIFO64", "ns16550a";
235 reg = <0x21d0600 0x100>;
236 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
237 clock-frequency = <0>;
242 lpuart0: serial@2950000 {
243 compatible = "fsl,ls1021a-lpuart";
244 reg = <0x2950000 0x1000>;
245 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
251 lpuart1: serial@2960000 {
252 compatible = "fsl,ls1021a-lpuart";
253 reg = <0x2960000 0x1000>;
254 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&platform_clk 1>;
260 lpuart2: serial@2970000 {
261 compatible = "fsl,ls1021a-lpuart";
262 reg = <0x2970000 0x1000>;
263 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&platform_clk 1>;
269 lpuart3: serial@2980000 {
270 compatible = "fsl,ls1021a-lpuart";
271 reg = <0x2980000 0x1000>;
272 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&platform_clk 1>;
278 lpuart4: serial@2990000 {
279 compatible = "fsl,ls1021a-lpuart";
280 reg = <0x2990000 0x1000>;
281 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&platform_clk 1>;
287 lpuart5: serial@29a0000 {
288 compatible = "fsl,ls1021a-lpuart";
289 reg = <0x29a0000 0x1000>;
290 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&platform_clk 1>;
296 wdog0: watchdog@2ad0000 {
297 compatible = "fsl,imx21-wdt";
298 reg = <0x2ad0000 0x10000>;
299 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&platform_clk 1>;
301 clock-names = "wdog-en";
306 compatible = "fsl,vf610-sai";
307 reg = <0x2b50000 0x10000>;
308 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&platform_clk 1>;
311 dma-names = "tx", "rx";
312 dmas = <&edma0 1 47>,
319 compatible = "fsl,vf610-sai";
320 reg = <0x2b60000 0x10000>;
321 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&platform_clk 1>;
324 dma-names = "tx", "rx";
325 dmas = <&edma0 1 45>,
331 edma0: edma@2c00000 {
333 compatible = "fsl,vf610-edma";
334 reg = <0x2c00000 0x10000>,
337 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
339 interrupt-names = "edma-tx", "edma-err";
342 clock-names = "dmamux0", "dmamux1";
343 clocks = <&platform_clk 1>,
347 mdio0: mdio@2d24000 {
348 compatible = "gianfar";
349 device_type = "mdio";
350 #address-cells = <1>;
352 reg = <0x2d24000 0x4000>;
356 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
357 reg = <0x8600000 0x1000>;
358 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
364 compatible = "snps,dwc3";
365 reg = <0x3100000 0x10000>;
366 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;