2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/omap.h>
16 compatible = "ti,omap3430", "ti,omap3";
17 interrupt-parent = <&intc>;
36 compatible = "arm,cortex-a8";
43 clock-latency = <300000>; /* From omap-cpufreq driver */
48 compatible = "arm,cortex-a8-pmu";
49 reg = <0x54000000 0x800000>;
51 ti,hwmods = "debugss";
55 * The soc node represents the soc top level view. It is used for IPs
56 * that are not memory mapped in the MPU view or for the MPU itself.
59 compatible = "ti,omap-infra";
61 compatible = "ti,omap3-mpu";
66 compatible = "ti,iva2.2";
70 compatible = "ti,omap3-c64";
76 * XXX: Use a flat representation of the OMAP3 interconnect.
77 * The real OMAP interconnect network is quite complex.
78 * Since it will not bring real advantage to represent that in DT for
79 * the moment, just use a fake OCP bus entry to represent the whole bus
83 compatible = "ti,omap3-l3-smx", "simple-bus";
84 reg = <0x68000000 0x10000>;
89 ti,hwmods = "l3_main";
91 l4_core: l4@48000000 {
92 compatible = "ti,omap3-l4-core", "simple-bus";
95 ranges = <0 0x48000000 0x1000000>;
98 compatible = "ti,omap3-scm", "simple-bus";
99 reg = <0x2000 0x2000>;
100 #address-cells = <1>;
102 ranges = <0 0x2000 0x2000>;
104 omap3_pmx_core: pinmux@30 {
105 compatible = "ti,omap3-padconf",
108 #address-cells = <1>;
110 #interrupt-cells = <1>;
111 interrupt-controller;
112 pinctrl-single,register-width = <16>;
113 pinctrl-single,function-mask = <0xff1f>;
116 scm_conf: scm_conf@270 {
117 compatible = "syscon", "simple-bus";
119 #address-cells = <1>;
121 ranges = <0 0x270 0x330>;
123 pbias_regulator: pbias_regulator@2b0 {
124 compatible = "ti,pbias-omap3", "ti,pbias-omap";
126 syscon = <&scm_conf>;
127 pbias_mmc_reg: pbias_mmc_omap2430 {
128 regulator-name = "pbias_mmc_omap2430";
129 regulator-min-microvolt = <1800000>;
130 regulator-max-microvolt = <3000000>;
135 #address-cells = <1>;
140 scm_clockdomains: clockdomains {
143 omap3_pmx_wkup: pinmux@a00 {
144 compatible = "ti,omap3-padconf",
147 #address-cells = <1>;
149 #interrupt-cells = <1>;
150 interrupt-controller;
151 pinctrl-single,register-width = <16>;
152 pinctrl-single,function-mask = <0xff1f>;
158 compatible = "ti,omap3-aes";
160 reg = <0x480c5000 0x50>;
162 dmas = <&sdma 65 &sdma 66>;
163 dma-names = "tx", "rx";
167 compatible = "ti,omap3-prm";
168 reg = <0x48306000 0x4000>;
172 #address-cells = <1>;
176 prm_clockdomains: clockdomains {
181 compatible = "ti,omap3-cm";
182 reg = <0x48004000 0x4000>;
185 #address-cells = <1>;
189 cm_clockdomains: clockdomains {
193 counter32k: counter@48320000 {
194 compatible = "ti,omap-counter32k";
195 reg = <0x48320000 0x20>;
196 ti,hwmods = "counter_32k";
199 intc: interrupt-controller@48200000 {
200 compatible = "ti,omap3-intc";
201 interrupt-controller;
202 #interrupt-cells = <1>;
203 reg = <0x48200000 0x1000>;
206 sdma: dma-controller@48056000 {
207 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
208 reg = <0x48056000 0x1000>;
218 gpio1: gpio@48310000 {
219 compatible = "ti,omap3-gpio";
220 reg = <0x48310000 0x200>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
230 gpio2: gpio@49050000 {
231 compatible = "ti,omap3-gpio";
232 reg = <0x49050000 0x200>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
241 gpio3: gpio@49052000 {
242 compatible = "ti,omap3-gpio";
243 reg = <0x49052000 0x200>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
252 gpio4: gpio@49054000 {
253 compatible = "ti,omap3-gpio";
254 reg = <0x49054000 0x200>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
263 gpio5: gpio@49056000 {
264 compatible = "ti,omap3-gpio";
265 reg = <0x49056000 0x200>;
270 interrupt-controller;
271 #interrupt-cells = <2>;
274 gpio6: gpio@49058000 {
275 compatible = "ti,omap3-gpio";
276 reg = <0x49058000 0x200>;
281 interrupt-controller;
282 #interrupt-cells = <2>;
285 uart1: serial@4806a000 {
286 compatible = "ti,omap3-uart";
287 reg = <0x4806a000 0x2000>;
289 interrupts-extended = <&intc 72>;
290 dmas = <&sdma 49 &sdma 50>;
291 dma-names = "tx", "rx";
293 clock-frequency = <48000000>;
296 uart2: serial@4806c000 {
297 compatible = "ti,omap3-uart";
298 reg = <0x4806c000 0x400>;
299 interrupts-extended = <&intc 73>;
300 dmas = <&sdma 51 &sdma 52>;
301 dma-names = "tx", "rx";
303 clock-frequency = <48000000>;
306 uart3: serial@49020000 {
307 compatible = "ti,omap3-uart";
308 reg = <0x49020000 0x400>;
309 interrupts-extended = <&intc 74>;
310 dmas = <&sdma 53 &sdma 54>;
311 dma-names = "tx", "rx";
313 clock-frequency = <48000000>;
317 compatible = "ti,omap3-i2c";
318 reg = <0x48070000 0x80>;
320 dmas = <&sdma 27 &sdma 28>;
321 dma-names = "tx", "rx";
322 #address-cells = <1>;
328 compatible = "ti,omap3-i2c";
329 reg = <0x48072000 0x80>;
331 dmas = <&sdma 29 &sdma 30>;
332 dma-names = "tx", "rx";
333 #address-cells = <1>;
339 compatible = "ti,omap3-i2c";
340 reg = <0x48060000 0x80>;
342 dmas = <&sdma 25 &sdma 26>;
343 dma-names = "tx", "rx";
344 #address-cells = <1>;
349 mailbox: mailbox@48094000 {
350 compatible = "ti,omap3-mailbox";
351 ti,hwmods = "mailbox";
352 reg = <0x48094000 0x200>;
355 ti,mbox-num-users = <2>;
356 ti,mbox-num-fifos = <2>;
358 ti,mbox-tx = <0 0 0>;
359 ti,mbox-rx = <1 0 0>;
363 mcspi1: spi@48098000 {
364 compatible = "ti,omap2-mcspi";
365 reg = <0x48098000 0x100>;
367 #address-cells = <1>;
369 ti,hwmods = "mcspi1";
379 dma-names = "tx0", "rx0", "tx1", "rx1",
380 "tx2", "rx2", "tx3", "rx3";
383 mcspi2: spi@4809a000 {
384 compatible = "ti,omap2-mcspi";
385 reg = <0x4809a000 0x100>;
387 #address-cells = <1>;
389 ti,hwmods = "mcspi2";
395 dma-names = "tx0", "rx0", "tx1", "rx1";
398 mcspi3: spi@480b8000 {
399 compatible = "ti,omap2-mcspi";
400 reg = <0x480b8000 0x100>;
402 #address-cells = <1>;
404 ti,hwmods = "mcspi3";
410 dma-names = "tx0", "rx0", "tx1", "rx1";
413 mcspi4: spi@480ba000 {
414 compatible = "ti,omap2-mcspi";
415 reg = <0x480ba000 0x100>;
417 #address-cells = <1>;
419 ti,hwmods = "mcspi4";
421 dmas = <&sdma 70>, <&sdma 71>;
422 dma-names = "tx0", "rx0";
425 hdqw1w: 1w@480b2000 {
426 compatible = "ti,omap3-1w";
427 reg = <0x480b2000 0x1000>;
433 compatible = "ti,omap3-hsmmc";
434 reg = <0x4809c000 0x200>;
438 dmas = <&sdma 61>, <&sdma 62>;
439 dma-names = "tx", "rx";
440 pbias-supply = <&pbias_mmc_reg>;
444 compatible = "ti,omap3-hsmmc";
445 reg = <0x480b4000 0x200>;
448 dmas = <&sdma 47>, <&sdma 48>;
449 dma-names = "tx", "rx";
453 compatible = "ti,omap3-hsmmc";
454 reg = <0x480ad000 0x200>;
457 dmas = <&sdma 77>, <&sdma 78>;
458 dma-names = "tx", "rx";
461 mmu_isp: mmu@480bd400 {
463 compatible = "ti,omap2-iommu";
464 reg = <0x480bd400 0x80>;
466 ti,hwmods = "mmu_isp";
467 ti,#tlb-entries = <8>;
470 mmu_iva: mmu@5d000000 {
472 compatible = "ti,omap2-iommu";
473 reg = <0x5d000000 0x80>;
475 ti,hwmods = "mmu_iva";
480 compatible = "ti,omap3-wdt";
481 reg = <0x48314000 0x80>;
482 ti,hwmods = "wd_timer2";
485 mcbsp1: mcbsp@48074000 {
486 compatible = "ti,omap3-mcbsp";
487 reg = <0x48074000 0xff>;
489 interrupts = <16>, /* OCP compliant interrupt */
490 <59>, /* TX interrupt */
491 <60>; /* RX interrupt */
492 interrupt-names = "common", "tx", "rx";
493 ti,buffer-size = <128>;
494 ti,hwmods = "mcbsp1";
497 dma-names = "tx", "rx";
498 clocks = <&mcbsp1_fck>;
503 mcbsp2: mcbsp@49022000 {
504 compatible = "ti,omap3-mcbsp";
505 reg = <0x49022000 0xff>,
507 reg-names = "mpu", "sidetone";
508 interrupts = <17>, /* OCP compliant interrupt */
509 <62>, /* TX interrupt */
510 <63>, /* RX interrupt */
512 interrupt-names = "common", "tx", "rx", "sidetone";
513 ti,buffer-size = <1280>;
514 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
517 dma-names = "tx", "rx";
518 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
519 clock-names = "fck", "ick";
523 mcbsp3: mcbsp@49024000 {
524 compatible = "ti,omap3-mcbsp";
525 reg = <0x49024000 0xff>,
527 reg-names = "mpu", "sidetone";
528 interrupts = <22>, /* OCP compliant interrupt */
529 <89>, /* TX interrupt */
530 <90>, /* RX interrupt */
532 interrupt-names = "common", "tx", "rx", "sidetone";
533 ti,buffer-size = <128>;
534 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
537 dma-names = "tx", "rx";
538 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
539 clock-names = "fck", "ick";
543 mcbsp4: mcbsp@49026000 {
544 compatible = "ti,omap3-mcbsp";
545 reg = <0x49026000 0xff>;
547 interrupts = <23>, /* OCP compliant interrupt */
548 <54>, /* TX interrupt */
549 <55>; /* RX interrupt */
550 interrupt-names = "common", "tx", "rx";
551 ti,buffer-size = <128>;
552 ti,hwmods = "mcbsp4";
555 dma-names = "tx", "rx";
556 clocks = <&mcbsp4_fck>;
561 mcbsp5: mcbsp@48096000 {
562 compatible = "ti,omap3-mcbsp";
563 reg = <0x48096000 0xff>;
565 interrupts = <27>, /* OCP compliant interrupt */
566 <81>, /* TX interrupt */
567 <82>; /* RX interrupt */
568 interrupt-names = "common", "tx", "rx";
569 ti,buffer-size = <128>;
570 ti,hwmods = "mcbsp5";
573 dma-names = "tx", "rx";
574 clocks = <&mcbsp5_fck>;
579 sham: sham@480c3000 {
580 compatible = "ti,omap3-sham";
582 reg = <0x480c3000 0x64>;
588 smartreflex_core: smartreflex@480cb000 {
589 compatible = "ti,omap3-smartreflex-core";
590 ti,hwmods = "smartreflex_core";
591 reg = <0x480cb000 0x400>;
595 smartreflex_mpu_iva: smartreflex@480c9000 {
596 compatible = "ti,omap3-smartreflex-iva";
597 ti,hwmods = "smartreflex_mpu_iva";
598 reg = <0x480c9000 0x400>;
602 timer1: timer@48318000 {
603 compatible = "ti,omap3430-timer";
604 reg = <0x48318000 0x400>;
606 ti,hwmods = "timer1";
610 timer2: timer@49032000 {
611 compatible = "ti,omap3430-timer";
612 reg = <0x49032000 0x400>;
614 ti,hwmods = "timer2";
617 timer3: timer@49034000 {
618 compatible = "ti,omap3430-timer";
619 reg = <0x49034000 0x400>;
621 ti,hwmods = "timer3";
624 timer4: timer@49036000 {
625 compatible = "ti,omap3430-timer";
626 reg = <0x49036000 0x400>;
628 ti,hwmods = "timer4";
631 timer5: timer@49038000 {
632 compatible = "ti,omap3430-timer";
633 reg = <0x49038000 0x400>;
635 ti,hwmods = "timer5";
639 timer6: timer@4903a000 {
640 compatible = "ti,omap3430-timer";
641 reg = <0x4903a000 0x400>;
643 ti,hwmods = "timer6";
647 timer7: timer@4903c000 {
648 compatible = "ti,omap3430-timer";
649 reg = <0x4903c000 0x400>;
651 ti,hwmods = "timer7";
655 timer8: timer@4903e000 {
656 compatible = "ti,omap3430-timer";
657 reg = <0x4903e000 0x400>;
659 ti,hwmods = "timer8";
664 timer9: timer@49040000 {
665 compatible = "ti,omap3430-timer";
666 reg = <0x49040000 0x400>;
668 ti,hwmods = "timer9";
672 timer10: timer@48086000 {
673 compatible = "ti,omap3430-timer";
674 reg = <0x48086000 0x400>;
676 ti,hwmods = "timer10";
680 timer11: timer@48088000 {
681 compatible = "ti,omap3430-timer";
682 reg = <0x48088000 0x400>;
684 ti,hwmods = "timer11";
688 timer12: timer@48304000 {
689 compatible = "ti,omap3430-timer";
690 reg = <0x48304000 0x400>;
692 ti,hwmods = "timer12";
697 usbhstll: usbhstll@48062000 {
698 compatible = "ti,usbhs-tll";
699 reg = <0x48062000 0x1000>;
701 ti,hwmods = "usb_tll_hs";
704 usbhshost: usbhshost@48064000 {
705 compatible = "ti,usbhs-host";
706 reg = <0x48064000 0x400>;
707 ti,hwmods = "usb_host_hs";
708 #address-cells = <1>;
712 usbhsohci: ohci@48064400 {
713 compatible = "ti,ohci-omap3";
714 reg = <0x48064400 0x400>;
715 interrupt-parent = <&intc>;
719 usbhsehci: ehci@48064800 {
720 compatible = "ti,ehci-omap";
721 reg = <0x48064800 0x400>;
722 interrupt-parent = <&intc>;
727 gpmc: gpmc@6e000000 {
728 compatible = "ti,omap3430-gpmc";
730 reg = <0x6e000000 0x02d0>;
735 gpmc,num-waitpins = <4>;
736 #address-cells = <2>;
738 interrupt-controller;
739 #interrupt-cells = <2>;
744 usb_otg_hs: usb_otg_hs@480ab000 {
745 compatible = "ti,omap3-musb";
746 reg = <0x480ab000 0x1000>;
747 interrupts = <92>, <93>;
748 interrupt-names = "mc", "dma";
749 ti,hwmods = "usb_otg_hs";
756 compatible = "ti,omap3-dss";
757 reg = <0x48050000 0x200>;
759 ti,hwmods = "dss_core";
760 clocks = <&dss1_alwon_fck>;
762 #address-cells = <1>;
767 compatible = "ti,omap3-dispc";
768 reg = <0x48050400 0x400>;
770 ti,hwmods = "dss_dispc";
771 clocks = <&dss1_alwon_fck>;
775 dsi: encoder@4804fc00 {
776 compatible = "ti,omap3-dsi";
777 reg = <0x4804fc00 0x200>,
780 reg-names = "proto", "phy", "pll";
783 ti,hwmods = "dss_dsi1";
784 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
785 clock-names = "fck", "sys_clk";
788 rfbi: encoder@48050800 {
789 compatible = "ti,omap3-rfbi";
790 reg = <0x48050800 0x100>;
792 ti,hwmods = "dss_rfbi";
793 clocks = <&dss1_alwon_fck>, <&dss_ick>;
794 clock-names = "fck", "ick";
797 venc: encoder@48050c00 {
798 compatible = "ti,omap3-venc";
799 reg = <0x48050c00 0x100>;
801 ti,hwmods = "dss_venc";
802 clocks = <&dss_tv_fck>;
807 ssi: ssi-controller@48058000 {
808 compatible = "ti,omap3-ssi";
813 reg = <0x48058000 0x1000>,
819 interrupt-names = "gdd_mpu";
821 #address-cells = <1>;
825 ssi_port1: ssi-port@4805a000 {
826 compatible = "ti,omap3-ssi-port";
828 reg = <0x4805a000 0x800>,
833 interrupt-parent = <&intc>;
838 ssi_port2: ssi-port@4805b000 {
839 compatible = "ti,omap3-ssi-port";
841 reg = <0x4805b000 0x800>,
846 interrupt-parent = <&intc>;
854 /include/ "omap3xxx-clocks.dtsi"