git.sur5r.net Git - u-boot/blob - arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi

   1 /*
   2  * Device Tree Source for OMAP34xx/OMAP36xx clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &cm_clocks {
  11        ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
  12                #clock-cells = <0>;
  13                compatible = "ti,composite-no-wait-gate-clock";
  14                clocks = <&corex2_fck>;
  15                ti,bit-shift = <0>;
  16                reg = <0x0a00>;
  17        };
  18
  19        ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
  20                #clock-cells = <0>;
  21                compatible = "ti,composite-divider-clock";
  22                clocks = <&corex2_fck>;
  23                ti,bit-shift = <8>;
  24                reg = <0x0a40>;
  25                ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
  26        };
  27
  28        ssi_ssr_fck: ssi_ssr_fck_3430es2 {
  29                #clock-cells = <0>;
  30                compatible = "ti,composite-clock";
  31                clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
  32        };
  33
  34        ssi_sst_fck: ssi_sst_fck_3430es2 {
  35                #clock-cells = <0>;
  36                compatible = "fixed-factor-clock";
  37                clocks = <&ssi_ssr_fck>;
  38                clock-mult = <1>;
  39                clock-div = <2>;
  40        };
  41
  42        hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
  43                #clock-cells = <0>;
  44                compatible = "ti,omap3-hsotgusb-interface-clock";
  45                clocks = <&core_l3_ick>;
  46                reg = <0x0a10>;
  47                ti,bit-shift = <4>;
  48        };
  49
  50        ssi_l4_ick: ssi_l4_ick {
  51                #clock-cells = <0>;
  52                compatible = "fixed-factor-clock";
  53                clocks = <&l4_ick>;
  54                clock-mult = <1>;
  55                clock-div = <1>;
  56        };
  57
  58        ssi_ick: ssi_ick_3430es2@a10 {
  59                #clock-cells = <0>;
  60                compatible = "ti,omap3-ssi-interface-clock";
  61                clocks = <&ssi_l4_ick>;
  62                reg = <0x0a10>;
  63                ti,bit-shift = <0>;
  64        };
  65
  66        usim_gate_fck: usim_gate_fck@c00 {
  67                #clock-cells = <0>;
  68                compatible = "ti,composite-gate-clock";
  69                clocks = <&omap_96m_fck>;
  70                ti,bit-shift = <9>;
  71                reg = <0x0c00>;
  72        };
  73
  74        sys_d2_ck: sys_d2_ck {
  75                #clock-cells = <0>;
  76                compatible = "fixed-factor-clock";
  77                clocks = <&sys_ck>;
  78                clock-mult = <1>;
  79                clock-div = <2>;
  80        };
  81
  82        omap_96m_d2_fck: omap_96m_d2_fck {
  83                #clock-cells = <0>;
  84                compatible = "fixed-factor-clock";
  85                clocks = <&omap_96m_fck>;
  86                clock-mult = <1>;
  87                clock-div = <2>;
  88        };
  89
  90        omap_96m_d4_fck: omap_96m_d4_fck {
  91                #clock-cells = <0>;
  92                compatible = "fixed-factor-clock";
  93                clocks = <&omap_96m_fck>;
  94                clock-mult = <1>;
  95                clock-div = <4>;
  96        };
  97
  98        omap_96m_d8_fck: omap_96m_d8_fck {
  99                #clock-cells = <0>;
 100                compatible = "fixed-factor-clock";
 101                clocks = <&omap_96m_fck>;
 102                clock-mult = <1>;
 103                clock-div = <8>;
 104        };
 105
 106        omap_96m_d10_fck: omap_96m_d10_fck {
 107                #clock-cells = <0>;
 108                compatible = "fixed-factor-clock";
 109                clocks = <&omap_96m_fck>;
 110                clock-mult = <1>;
 111                clock-div = <10>;
 112        };
 113
 114        dpll5_m2_d4_ck: dpll5_m2_d4_ck {
 115                #clock-cells = <0>;
 116                compatible = "fixed-factor-clock";
 117                clocks = <&dpll5_m2_ck>;
 118                clock-mult = <1>;
 119                clock-div = <4>;
 120        };
 121
 122        dpll5_m2_d8_ck: dpll5_m2_d8_ck {
 123                #clock-cells = <0>;
 124                compatible = "fixed-factor-clock";
 125                clocks = <&dpll5_m2_ck>;
 126                clock-mult = <1>;
 127                clock-div = <8>;
 128        };
 129
 130        dpll5_m2_d16_ck: dpll5_m2_d16_ck {
 131                #clock-cells = <0>;
 132                compatible = "fixed-factor-clock";
 133                clocks = <&dpll5_m2_ck>;
 134                clock-mult = <1>;
 135                clock-div = <16>;
 136        };
 137
 138        dpll5_m2_d20_ck: dpll5_m2_d20_ck {
 139                #clock-cells = <0>;
 140                compatible = "fixed-factor-clock";
 141                clocks = <&dpll5_m2_ck>;
 142                clock-mult = <1>;
 143                clock-div = <20>;
 144        };
 145
 146        usim_mux_fck: usim_mux_fck@c40 {
 147                #clock-cells = <0>;
 148                compatible = "ti,composite-mux-clock";
 149                clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
 150                ti,bit-shift = <3>;
 151                reg = <0x0c40>;
 152                ti,index-starts-at-one;
 153        };
 154
 155        usim_fck: usim_fck {
 156                #clock-cells = <0>;
 157                compatible = "ti,composite-clock";
 158                clocks = <&usim_gate_fck>, <&usim_mux_fck>;
 159        };
 160
 161        usim_ick: usim_ick@c10 {
 162                #clock-cells = <0>;
 163                compatible = "ti,omap3-interface-clock";
 164                clocks = <&wkup_l4_ick>;
 165                reg = <0x0c10>;
 166                ti,bit-shift = <9>;
 167        };
 168 };
 169
 170 &cm_clockdomains {
 171        core_l3_clkdm: core_l3_clkdm {
 172                compatible = "ti,clockdomain";
 173                clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
 174        };
 175
 176        wkup_clkdm: wkup_clkdm {
 177                compatible = "ti,clockdomain";
 178                clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
 179                         <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
 180                         <&gpt1_ick>, <&usim_ick>;
 181        };
 182
 183        core_l4_clkdm: core_l4_clkdm {
 184                compatible = "ti,clockdomain";
 185                clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
 186                         <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
 187                         <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
 188                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
 189                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
 190                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
 191                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
 192                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
 193                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
 194                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
 195                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
 196                         <&ssi_ick>;
 197        };
 198 };